Invention Grant
US08321828B2 Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance
有权
虚拟填充以减少晶体管性能的浅沟槽隔离(STI)应力变化
- Patent Title: Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance
- Patent Title (中): 虚拟填充以减少晶体管性能的浅沟槽隔离(STI)应力变化
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Application No.: US12684819Application Date: 2010-01-08
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Publication No.: US08321828B2Publication Date: 2012-11-27
- Inventor: Chan-Hong Chern
- Applicant: Chan-Hong Chern
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of forming an integrated circuit structure on a chip includes extracting an active layer from a design of the integrated circuit structure, forming a guard band conforming to the shape of the active layer, the guard band surrounds the active layer, and the guard band is spaced from the active layer at a first spacing in the X-axis direction and at a second spacing in the Y-axis direction, removing any part of the guard band that violates design rules, removing convex corners of the guard band, and adding dummy diffusion patterns into the remaining space of the chip outside the guard band. The first and second spacing can be specified as the same spacings in a Spice model characterization of the integrated circuit structure. The dummy diffusion patterns with different granularities can be added so that the diffusion density is substantially uniform over the chip.
Public/Granted literature
- US20100223585A1 DUMMY FILL TO REDUCE SHALLOW TRENCH ISOLATION (STI) STRESS VARIATION ON TRANSISTOR PERFORMANCE Public/Granted day:2010-09-02
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