A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection circuit configured to detect a number of selected planes of the plurality of planes, and a resistance variable circuit configured to vary a wiring resistance between the plurality of planes and the voltage generating circuit in accordance with the number of selected planes, which is reported from the select number detection circuit, and a control circuit configured to control the power supply voltage generating circuit.