公开(公告)号：US20240250163A1

公开(公告)日：2024-07-25

申请号：US18429202

申请日：2024-01-31

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach

IPC分类号： H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B63/00 ,  H10B69/00

CPC分类号： H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

摘要： 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

公开(公告)号：US20240249106A1

公开(公告)日：2024-07-25

申请号：US18624312

申请日：2024-04-02

申请人： Kioxia Corporation

发明人： Akihisa FUJIMOTO ,  Toshitada SAITO ,  Noriya SAKAMOTO ,  Atsushi KONDO

IPC分类号： G06K19/077 ,  G11C5/06 ,  G11C11/4074 ,  G11C16/02 ,  G11C16/30

CPC分类号： G06K19/07732 ,  G06K19/07733 ,  G06K19/07743 ,  G11C5/06 ,  G11C11/4074 ,  G11C16/02 ,  G11C16/30

摘要： According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1st to Nth terminal groups. The first surface includes first to Nth rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1st to Nth terminal groups are placed in the first to Nth rows. The 1st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kth terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

公开(公告)号：US11935949B1

公开(公告)日：2024-03-19

申请号：US18388852

申请日：2023-11-12

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach

IPC分类号： H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B63/00 ,  H10B69/00

CPC分类号： H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

摘要： 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

公开(公告)号：US11594281B2

公开(公告)日：2023-02-28

申请号：US17154241

申请日：2021-01-21

申请人： Mosaid Technologies Incorporated

发明人： Chung-Zen Chen ,  Yang-Chieh Lin ,  Chung-Shan Kuo

IPC分类号： G11C16/14 ,  G11C16/16 ,  G11C16/08 ,  G11C16/02 ,  G11C16/04

摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

公开(公告)号：US11575038B1

公开(公告)日：2023-02-07

申请号：US17961565

申请日：2022-10-07

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach

IPC分类号： H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11 ,  H01L27/11578 ,  H01L27/24 ,  G11C11/412 ,  G11C16/04

摘要： A 3D semiconductor device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one first metal layer, where the at least one first metal layer overlays the first single crystal layer, and where the at least one first metal layer includes interconnects between the first transistors forming first control circuits; a second metal layer overlaying the at least one first metal layer; a second level overlaying the second metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes second memory cells, the second memory cells each including third transistors.

公开(公告)号：US20230033173A1

公开(公告)日：2023-02-02

申请号：US17961565

申请日：2022-10-07

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach

IPC分类号： H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11 ,  H01L27/11578 ,  H01L27/24

摘要： A 3D semiconductor device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one first metal layer, where the at least one first metal layer overlays the first single crystal layer, and where the at least one first metal layer includes interconnects between the first transistors forming first control circuits; a second metal layer overlaying the at least one first metal layer; a second level overlaying the second metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes second memory cells, the second memory cells each including third transistors.

公开(公告)号：US11004967B1

公开(公告)日：2021-05-11

申请号：US17176146

申请日：2021-02-15

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach

IPC分类号： H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11 ,  H01L27/11578 ,  H01L27/24 ,  G11C11/412 ,  G11C16/04

摘要： A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

公开(公告)号：US10720433B2

公开(公告)日：2020-07-21

申请号：US15728797

申请日：2017-10-10

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Keitaro Imai ,  Jun Koyama

IPC分类号： H01L27/108 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/088 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L29/786 ,  H01L27/092

摘要： The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

公开(公告)号：US20190131973A1

公开(公告)日：2019-05-02

申请号：US15876693

申请日：2018-01-22

申请人： Synopsys, Inc.

发明人： Vijay A. NEBHRAJANI ,  Sanket NAIK

IPC分类号： H03K19/177 ,  G01R31/3185 ,  G11C16/02

摘要： Programmable shift register with programmable load location (pSRL) for data storage and method thereof is disclosed. A loadable programmable Shift Register (pSR) according to present disclosure receives a programmable input LL that defines where data D is to be loaded from the Load Register when L (Load Control Signal)=1. The loadable Shift Register with programmable load location (pSRL) is configured to obtain L (Load Control Signal), S (Shift Control Signal), LL (Load Location Control Signal), and p (programmable shift value), and wherein the pSRL is adapted to perform loading and shifting of data D based at least on the L, S, LL, and p values.

公开(公告)号：US10210934B2

公开(公告)日：2019-02-19

申请号：US15893625

申请日：2018-02-10

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  G11C16/04 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  G11C11/56 ,  G11C16/02 ,  H01L29/792

摘要： A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.