发明授权
- 专利标题： Scheduling control within a data processing system
- 专利标题（中）： 数据处理系统内的调度控制
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申请号： US12458699申请日： 2009-07-21
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公开(公告)号： US08327118B2公开(公告)日： 2012-12-04
- 发明人: David Michael Bull , Emre Ozer , Shidhartha Das
- 申请人： David Michael Bull , Emre Ozer , Shidhartha Das
- 申请人地址： GB Cambridge
- 专利权人： ARM Limited
- 当前专利权人： ARM Limited
- 当前专利权人地址： GB Cambridge
- 代理机构： Nixon & Vanderhye P.C.
- 优先权： GB0816296.8 20080905
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; G06F9/40 ; G06F15/00
摘要：
A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.
公开/授权文献
- US20100064287A1 Scheduling control within a data processing system 公开/授权日：2010-03-11
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