公开(公告)号：US20100275080A1

公开(公告)日：2010-10-28

申请号：US12735339

申请日：2008-12-29

申请人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

发明人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

IPC分类号： G06F11/07

CPC分类号： G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

摘要： An integrated circuit (2) is provided with error detection circuitry (10,12) and error repair circuitry (14). Error tolerance circuitry (16) is responsive to a control parameter to selectively disable the error repair circuitry (14). The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behaviour of the circuit or in other ways.

摘要翻译： 集成电路（2）具有错误检测电路（10,12）和错误修复电路（14）。 误差容限电路（16）响应于控制参数来选择性地禁用误差修复电路（14）。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

公开(公告)号：US08327118B2

公开(公告)日：2012-12-04

申请号：US12458699

申请日：2009-07-21

申请人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

发明人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3891 ,  G06F11/004 ,  G06F11/1405

摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.

摘要翻译： 处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。 执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。 调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。

公开(公告)号：US08621272B2

公开(公告)日：2013-12-31

申请号：US12735339

申请日：2008-12-29

申请人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

发明人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

摘要： An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

公开(公告)号：US20120131313A1

公开(公告)日：2012-05-24

申请号：US13067510

申请日：2011-06-06

申请人： Emre Ozer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Ozer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.

摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新 流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联， 这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值 程序指令。 这样可以避免冲洗。

公开(公告)号：US20100064287A1

公开(公告)日：2010-03-11

申请号：US12458699

申请日：2009-07-21

申请人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

发明人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

IPC分类号： G06F9/30 ,  G06F11/07 ,  G06F9/46

CPC分类号： G06F9/3836 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3891 ,  G06F11/004 ,  G06F11/1405

摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.

摘要翻译： 处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。 执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。 调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。

公开(公告)号：US20080250271A1

公开(公告)日：2008-10-09

申请号：US12076165

申请日：2008-03-14

申请人： Emre Ozer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Ozer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F11/07

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.

摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6刷新上游程序指令。 当多线程时，需要从指令流水线6清除来自包括作为错误恢复的结果而丢失的指令的线程的那些指令。 还可以根据诸如特权级别，依赖指令数量等的特性来选择指令。指令流水线可以附加地/替代地设置有与这些主存储器相关联的多个信号值的多于一个的主存储元件26,28 元件26,28以交替方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获与以下程序指令相对应的信号值。 这样可以避免冲洗。

公开(公告)号：US20090106616A1

公开(公告)日：2009-04-23

申请号：US12285796

申请日：2008-10-14

申请人： Emre Ozer ,  David Michael Bull ,  Shidhartha Das

发明人： Emre Ozer ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/07

CPC分类号： G06F9/3842 ,  G06F9/3861 ,  G06F9/3869

摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.

摘要翻译： 集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗） 基于错误。 流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。 该预测用于触发第二次错误恢复操作（部分流水线停止）。 该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

公开(公告)号：US20100064109A1

公开(公告)日：2010-03-11

申请号：US12232188

申请日：2008-09-11

申请人： David Michael Bull ,  Emre Ozer

发明人： David Michael Bull ,  Emre Ozer

IPC分类号： G06F12/02

CPC分类号： G06F12/126 ,  G06F9/3806 ,  G06F9/3851

摘要： A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item.

摘要翻译： 提供了一种数据处理装置，包括用于执行多个程序线程的处理电路。 至少一个存储单元在多个程序线程之间共享并且包括多个条目，每个条目用于存储与高优先级程序线程或较低优先级程序线程相关联的存储项目。 还提供了用于保存存储单元的多个块中的每一个的历史字段的历史存储器。 在检测到作为对较低优先级存储项目的该条目的分配的结果被从存储单元驱逐的高优先级存储项目时，包含该条目的块的历史字段填充有被驱逐的高优先级存储项目的指示 。 当稍后将高优先级存储项目分配给存储单元的所选条目时，执行所分配的高优先级存储项目与包含所选择的条目的块的历史字段中的指示之间的比较操作，并且在检测到 匹配条件与该条目相关联的锁定指示被设置为禁止进一步驱逐该高优先级存储项目。

公开(公告)号：US20080209133A1

公开(公告)日：2008-08-28

申请号：US11709279

申请日：2007-02-22

申请人： Emre Ozer ,  Stuart David Biles ,  Simon Andrew Ford

发明人： Emre Ozer ,  Stuart David Biles ,  Simon Andrew Ford

IPC分类号： G06F13/00

CPC分类号： G06F12/0831 ,  G06F12/0822 ,  Y02D10/13

摘要： A data processing apparatus and method are provided for managing cache coherency. The data processing apparatus comprises a plurality of processing units, each having a cache associated therewith, and each cache having indication circuitry containing segment filtering data. The indication circuitry is responsive to an address portion of an address specified by an access request from an associated processing unit to reference the segment filtering data in order to provide, for each of at least a subset of the segments of the associated cache, an indication as to whether the data is either definitely not stored in that segment or is potentially stored in that segment. Further, in accordance with the present invention, cache coherency circuitry is provided which employs a cache coherency protocol to ensure data accessed by each processing unit is up-to-date. The cache coherency circuitry has snoop indication circuitry associated therewith whose content is derived from the segment filtering data of each indication circuitry. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry is referenced to determine whether any of the caches require subjecting to a snoop operation. For each cache for which it is determined a snoop operation should be performed, the cache coherency circuitry is arranged to issue a notification to that cache identifying the snoop operation to be performed. By taking advantage of information already provided in association with each cache in order to form the content of the snoop indication circuitry, significant hardware cost savings are achieved when compared with prior art techniques. Further, through use of such an approach, it is possible in embodiments of the present invention to identify the snoop operation not only on a cache-by-cache basis, but also for a particular cache to identify which segments of that cache should be subjected to the snoop operation.

公开(公告)号：US20090138890A1

公开(公告)日：2009-05-28

申请号：US12292565

申请日：2008-11-20

申请人： Geoffrey Blake ,  Trevor Nigel Mudge ,  Stuart David Biles ,  Nathan Yong Seng Chong ,  Emre Ozer ,  Ronald George Dreslinski

发明人： Geoffrey Blake ,  Trevor Nigel Mudge ,  Stuart David Biles ,  Nathan Yong Seng Chong ,  Emre Ozer ,  Ronald George Dreslinski

IPC分类号： G06F9/46

CPC分类号： G06F9/467 ,  G06F9/30087 ,  G06F9/466 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/621

摘要： A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.