发明授权
- 专利标题: Voltage drop aware circuit placement
- 专利标题(中): 电压降感知电路放置
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申请号: US12534053申请日: 2009-07-31
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公开(公告)号: US08327305B1公开(公告)日: 2012-12-04
- 发明人: Woi Jie Hooi , Teik Wah Lim , Ket Chiew Sia
- 申请人: Woi Jie Hooi , Teik Wah Lim , Ket Chiew Sia
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Womble Carlyle Sandridge & Rice, LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A circuit and methods for placing a circuit block on an integrated circuit (IC) are disclosed. An embodiment of the disclosed method includes dividing the IC into multiple regions based on pre-determined value. This pre-determined value may be a voltage drop value measured on specific regions on the IC. The performance requirement for the circuit block is determined and placed in one of the regions on the IC. In one embodiment, the placement of the circuit block is based on the performance requirement and the measured value at specific regions on the IC. The measured value may be a voltage drop value and a circuit block with a higher performance may be placed in a region with a lower voltage drop value.
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