发明授权
US08332788B1 Generating a module interface for partial reconfiguration design flows
有权
生成部分重新配置设计流程的模块接口
- 专利标题： Generating a module interface for partial reconfiguration design flows
- 专利标题（中）： 生成部分重新配置设计流程的模块接口
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申请号： US13077544申请日： 2011-03-31
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公开(公告)号： US08332788B1公开(公告)日： 2012-12-11
- 发明人: Jay T. Young , W. Story Leavesley, III
- 申请人： Jay T. Young , W. Story Leavesley, III
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 Kevin T. Cuenot; Lois D. Cartier
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A method of processing a logical netlist for implementing a circuit design within a programmable integrated circuit includes identifying a dynamically reconfigurable module (DRM) comprising a port from the logical netlist. The DRM defines a dynamically reconfigurable region of the integrated circuit that communicates with a module that is not dynamically reconfigurable via the port. First circuitry of the DRM and circuitry external to the DRM are implemented. The first circuitry connects to the circuitry external to the DRM via the port. The circuitry external to the DRM is within the module that is not dynamically reconfigurable. The method further includes locking routing resources connecting the circuitry external to the DRM to a location associated with a boundary of the DRM for the port; and implementing second circuitry of the DRM by reusing the locked routing resources. The second circuitry is routed to connect to the location associated with the boundary of the DRM for the port.
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