Invention Grant
- Patent Title: Computationally efficient modeling and simulation of large scale systems
- Patent Title (中): 大规模系统的计算效率建模与仿真
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Application No.: US12852942Application Date: 2010-08-09
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Publication No.: US08336014B1Publication Date: 2012-12-18
- Inventor: Jitesh Jain , Stephen F. Cauley , Hong Li , Cheng-Kok Koh , Venkataramanan Balakrishnan
- Applicant: Jitesh Jain , Stephen F. Cauley , Hong Li , Cheng-Kok Koh , Venkataramanan Balakrishnan
- Applicant Address: US IN West Lafayette
- Assignee: Purdue Research Foundation
- Current Assignee: Purdue Research Foundation
- Current Assignee Address: US IN West Lafayette
- Agency: Maginot, Moore & Beck LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X−1 and at least one other matrix, with first equation including X−1Y, X−1A, and X−1P, and the second equation including X−1A and X−1P.
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