发明授权
US08341569B2 Statistical iterative timing analysis of circuits having latches and/or feedback loops
有权
具有锁存器和/或反馈回路的电路的统计迭代时序分析
- 专利标题： Statistical iterative timing analysis of circuits having latches and/or feedback loops
- 专利标题（中）： 具有锁存器和/或反馈回路的电路的统计迭代时序分析
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申请号： US12842268申请日： 2010-07-23
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公开(公告)号： US08341569B2公开(公告)日： 2012-12-25
- 发明人: Lizheng Zhang , Yuhen Hu , Chun-ping Chen
- 申请人： Lizheng Zhang , Yuhen Hu , Chun-ping Chen
- 申请人地址： US WI Madison
- 专利权人： Wisconsin Alumni Research Foundation
- 当前专利权人： Wisconsin Alumni Research Foundation
- 当前专利权人地址： US WI Madison
- 代理机构： DeWitt Ross & Stevens S.C.
- 代理商 Craig A. Fieschko, Esq.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.
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