公开(公告)号：US08341569B2

公开(公告)日：2012-12-25

申请号：US12842268

申请日：2010-07-23

申请人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

发明人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

摘要翻译： 描述了具有锁存器和反馈回路的电路的统计时序分析方法，其中电路产量和/或临界循环平均值（电路中所有回路中的最大周期平均值）可以以高速度和精确度迭代地计算，从而允许 它们在拟议的电路设计的分析和验证中的准备使用。

公开(公告)号：US20100313177A1

公开(公告)日：2010-12-09

申请号：US12842268

申请日：2010-07-23

申请人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

发明人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

IPC分类号： G06F9/455

CPC分类号： G06F17/5031

摘要： Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

摘要翻译： 描述了具有锁存器和反馈回路的电路的统计时序分析方法，其中电路产量和/或临界循环平均值（电路中所有回路中的最大周期平均值）可以以高速度和精确度迭代地计算，从而允许 它们在拟议的电路设计的分析和验证中的准备使用。

公开(公告)号：US07793245B2

公开(公告)日：2010-09-07

申请号：US11966265

申请日：2007-12-28

申请人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

发明人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

摘要翻译： 描述了具有锁存器和反馈回路的电路的统计时序分析方法，其中电路产量和/或临界循环平均值（电路中所有回路中的最大周期平均值）可以以高速度和精确度迭代地计算，从而允许 它们在拟议的电路设计的分析和验证中的准备使用。

公开(公告)号：US20090055785A1

公开(公告)日：2009-02-26

申请号：US11966265

申请日：2007-12-28

申请人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

发明人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

摘要翻译： 描述了具有锁存器和反馈回路的电路的统计时序分析方法，其中电路产量和/或临界循环平均值（电路中所有回路中的最大周期平均值）可以以高速度和精确度迭代地计算，从而允许 它们在拟议的电路设计的分析和验证中的准备使用。

公开(公告)号：US07350171B2

公开(公告)日：2008-03-25

申请号：US11282003

申请日：2005-11-17

申请人： Lizheng Zhang ,  YuHen Hu ,  Chun-ping Chen

发明人： Lizheng Zhang ,  YuHen Hu ,  Chun-ping Chen

IPC分类号： G06F17/50 ,  G06F17/15 ,  G06F17/18

CPC分类号： G06F17/5031

摘要： Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An extended canonical timing model is used to represent each delay element along a circuit path, wherein the model bears information regarding any correlations that each element has to any other elements in the circuit (and/or to any external global factors, e.g., global temperature variations over the circuit, etc.). The model can be represented in a vectorized format which allows enhancement of computational efficiency, wherein the coefficients of the vectors allow an objective measure of element correlation (and wherein the vectors can be “pruned” by dropping insignificant coefficients to further enhance computational efficiency). A decomposition procedure can be used to decompose correlated elements into uncorrelated elements to allow delays to me more easily propagated through the timing diagram representing the circuit. Finally, a bounded approximation for the output of the MAX operator is described which provides a safely conservative approximation regardless of the linearity of the MAX output.

摘要翻译： 描述了用于补偿具有高计算效率的具有相关定时延迟的电路元件的电路的统计时序分析方法。 扩展规范定时模型用于表示沿着电路路径的每个延迟元件，其中模型承载关于每个元件对电路中的任何其他元件（和/或任何外部全局因素，例如全局温度）的任何相关性的信息 电路上的变化等）。 该模型可以以允许增强计算效率的向量化格式表示，其中矢量的系数允许元素相关性的客观测量（并且其中可以通过丢弃不重要的系数来“修剪”矢量以进一步提高计算效率）。 分解过程可以用于将相关元素分解为不相关元素，以允许延迟通过表示电路的时序图更容易地传播。 最后，描述了MAX运算器的输出的有界近似，其提供了安全保守的近似，而与MAX输出的线性无关。

公开(公告)号：US07689954B2

公开(公告)日：2010-03-30

申请号：US11420322

申请日：2006-05-25

申请人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

发明人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/504 ,  G06F2217/10 ,  G06F2217/84

摘要： Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An quadratic timing model is used to represent each delay element along a circuit path, wherein each element's delay has a first-order relationship to local variations and a second-order relationship to global variations. Propagation of the modeled delays through the circuit is efficiently done via straightforward ADD operations where an input propagates through another element in a circuit path, and via a MAX operation (or an approximation thereof) where two or more inputs merge at an intersection. The inputs to the MAX operator can be tested for gaussianity, and can be processed by the MAX operation (or its approximation) if they are substantially gaussian. Otherwise, they may be stored in a tuple for processing at later points along the circuit path.

摘要翻译： 描述了用于补偿具有高计算效率的具有相关定时延迟的电路元件的电路的统计时序分析方法。 二次定时模型用于沿着电路路径表示每个延迟元件，其中每个元件的延迟与局部变化和与全局变化的二阶关系具有一级关系。 经由电路的建模延迟的传播通过简单的ADD操作有效地进行，其中输入传播通过电路路径中的另一元件，并且经由其中两个或多个输入在交叉点合并的MAX操作（或其近似）。 可以对MAX运算符的输入进行高斯测试，如果MAX操作基本为高斯，则可以通过MAX操作（或其近似）进行处理。 否则，它们可以存储在元组中，以便在沿着电路路径的稍后点进行处理。

公开(公告)号：US20070277134A1

公开(公告)日：2007-11-29

申请号：US11420322

申请日：2006-05-25

申请人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

发明人： Lizheng Zhang ,  Yuhen Hu ,  Chun-ping Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/504 ,  G06F2217/10 ,  G06F2217/84

摘要： Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An quadratic timing model is used to represent each delay element along a circuit path, wherein each element's delay has a first-order relationship to local variations and a second-order relationship to global variations. Propagation of the modeled delays through the circuit is efficiently done via straightforward ADD operations where an input propagates through another element in a circuit path, and via a MAX operation (or an approximation thereof) where two or more inputs merge at an intersection. The inputs to the MAX operator can be tested for gaussianity, and can be processed by the MAX operation (or its approximation) if they are substantially gaussian. Otherwise, they may be stored in a tuple for processing at later points along the circuit path.

摘要翻译： 描述了用于补偿具有高计算效率的具有相关定时延迟的电路元件的电路的统计时序分析方法。 二次定时模型用于沿着电路路径表示每个延迟元件，其中每个元件的延迟与局部变化和与全局变化的二阶关系具有一级关系。 经由电路的建模延迟的传播通过简单的ADD操作有效地进行，其中输入传播通过电路路径中的另一元件，并且经由其中两个或多个输入在交叉点合并的MAX操作（或其近似）。 可以对MAX运算符的输入进行高斯测试，如果MAX操作基本为高斯，则可以通过MAX操作（或其近似）进行处理。 否则，它们可以存储在元组中，以便在沿着电路路径的稍后点进行处理。

公开(公告)号：US20070113211A1

公开(公告)日：2007-05-17

申请号：US11282003

申请日：2005-11-17

申请人： Lizheng Zhang ,  YuHen Hu ,  Chun-ping Chen

发明人： Lizheng Zhang ,  YuHen Hu ,  Chun-ping Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An extended canonical timing model is used to represent each delay element along a circuit path, wherein the model bears information regarding any correlations that each element has to any other elements in the circuit (and/or to any external global factors, e.g., global temperature variations over the circuit, etc.). The model can be represented in a vectorized format which allows enhancement of computational efficiency, wherein the coefficients of the vectors allow an objective measure of element correlation (and wherein the vectors can be “pruned” by dropping insignificant coefficients to further enhance computational efficiency). A decomposition procedure can be used to decompose correlated elements into uncorrelated elements to allow delays to me more easily propagated through the timing diagram representing the circuit. Finally, a bounded approximation for the output of the MAX operator is described which provides a safely conservative approximation regardless of the linearity of the MAX output.

摘要翻译： 描述了用于补偿具有高计算效率的具有相关定时延迟的电路元件的电路的统计时序分析方法。 扩展规范定时模型用于表示沿着电路路径的每个延迟元件，其中模型承载关于每个元件对电路中的任何其他元件（和/或任何外部全局因素，例如全局温度）的任何相关性的信息 电路上的变化等）。 该模型可以以允许增强计算效率的向量化格式表示，其中矢量的系数允许元素相关性的客观测量（并且其中可以通过丢弃不重要的系数来“修剪”矢量以进一步提高计算效率）。 分解过程可以用于将相关元素分解为不相关元素，以允许延迟通过表示电路的时序图更容易地传播。 最后，描述了MAX运算器的输出的有界近似，其提供了安全保守的近似，而与MAX输出的线性无关。