发明授权
US08345481B2 NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array
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基于NAND的NMOS NOR闪存单元,基于NAND的NMOS NOR闪存阵列,以及形成基于NAND的NMOS NOR闪存阵列的方法
- 专利标题: NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array
- 专利标题(中): 基于NAND的NMOS NOR闪存单元,基于NAND的NMOS NOR闪存阵列,以及形成基于NAND的NMOS NOR闪存阵列的方法
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申请号: US13317678申请日: 2011-10-25
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公开(公告)号: US08345481B2公开(公告)日: 2013-01-01
- 发明人: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- 申请人: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- 申请人地址: US CA San Jose
- 专利权人: Aplus Flash Technology, Inc.
- 当前专利权人: Aplus Flash Technology, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Saile Ackerman LLC
- 代理商 Stephen B. Ackerman; Billy Knowles
- 主分类号: G11C11/34
- IPC分类号: G11C11/34
摘要:
A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
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