Invention Grant
- Patent Title: Shielding techniques for an integrated circuit
- Patent Title (中): 集成电路的屏蔽技术
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Application No.: US12911171Application Date: 2010-10-25
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Publication No.: US08349710B2Publication Date: 2013-01-08
- Inventor: Yonggang Jin
- Applicant: Yonggang Jin
- Applicant Address: SG Singapore
- Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
- Current Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Wolf, Greenfield & Sacks, P.C.
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L21/78 ; H01L21/302

Abstract:
Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches.
Public/Granted literature
- US20120098104A1 SHIELDING TECHNIQUES FOR AN INTEGRATED CIRCUIT Public/Granted day:2012-04-26
Information query
IPC分类: