公开(公告)号：US08912653B2

公开(公告)日：2014-12-16

申请号：US13327563

申请日：2011-12-15

Applicant: Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

Inventor： Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

IPC: H01L23/52 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/00 ,  H01L21/311 ,  H01L23/31

CPC classification number: H01L21/3105 ,  H01L21/31116 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.

Abstract translation: 半导体晶片具有形成在其上的集成电路和施加的顶部钝化层。 钝化层被图案化并选择性地蚀刻以暴露每个半导体管芯上的接触焊盘。 将晶片暴露于电离气体中，导致钝化层的上表面变粗糙，并使接触垫的上表面略微变糙。 切割晶片以形成多个具有粗糙化钝化层的半导体管芯。 多个半导体管芯被放置在粘合剂层上并形成重构的晶片。 形成再分布层，以完成具有用于建立半导体封装外部的电连接的电触头的半导体封装，之后将晶片单分割以分离晶片。

公开(公告)号：US20130105973A1

公开(公告)日：2013-05-02

申请号：US13287826

申请日：2011-11-02

Applicant: Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

Inventor： Kah Wee Gan ,  Yaohuang Huang ,  Yonggang Jin

IPC: H01L23/485 ,  H01L21/56 ,  H01L21/58

CPC classification number: H01L23/48 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: An eWLB package for 3D and PoP applications includes a redistribution layer on a support wafer. A semiconductor die is coupled to the redistribution layer, and solder balls are also positioned on the redistribution layer. The die and solder balls are encapsulated in a molding compound layer, which is planarized to expose top portions of the solder balls. A second redistribution layer is formed on the planarized surface of the molding compound layer. A ball grid array can be positioned on the second redistribution layer to couple the semiconductor package to a circuit board, or additional semiconductor dies can be added, each in a respective molding compound layer. The support wafer can act as an interposer, in which case it is processed to form TSVs in electrical contact with the first redistribution layer, and a redistribution layer is formed on the opposite side of the support substrate, as well.

Abstract translation: 用于3D和PoP应用的eWLB封装包括支撑晶片上的再分配层。 半导体管芯耦合到再分配层，并且焊球也位于再分配层上。 模具和焊球被封装在模制化合物层中，其被平坦化以暴露焊球的顶部部分。 在模塑料层的平坦化表面上形成第二重分布层。 球栅阵列可以位于第二再分配层上以将半导体封装耦合到电路板，或者可以在相应的模制化合物层中添加另外的半导体管芯。 支撑晶片可以用作插入件，在这种情况下，它被处理以形成与第一再分配层电接触的TSV，并且再分配层也形成在支撑衬底的相对侧上。

公开(公告)号：US20100167471A1

公开(公告)日：2010-07-01

申请号：US12495734

申请日：2009-06-30

Applicant: Yonggang Jin ,  Xavier Baraton ,  Faxing Che

Inventor： Yonggang Jin ,  Xavier Baraton ,  Faxing Che

IPC: H01L21/56 ,  H01L21/60

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

Abstract translation: 扇出晶片级封装包括具有顶表面，底表面，多个侧表面以及限定在顶表面上的接合焊盘的集成电路。 密封剂层基本上围绕集成电路的侧表面，密封剂层的高度基本上等于集成电路的高度。 凸块与集成电路间隔开，并且再分配层将集成电路的接合焊盘电耦合到凸块。

公开(公告)号：US07443039B2

公开(公告)日：2008-10-28

申请号：US11306352

申请日：2005-12-23

Applicant: Lun Zhao ,  Wan Lay Looi ,  Kyaw Oo Aung ,  Yonggang Jin ,  Jae-Yong Song ,  Won Sun Shin

Inventor： Lun Zhao ,  Wan Lay Looi ,  Kyaw Oo Aung ,  Yonggang Jin ,  Jae-Yong Song ,  Won Sun Shin

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is over the substrate. A second metallurgy layer is over the first metallurgy layer. A protective layer is over the first contact pad.

Abstract translation: 集成电路封装设置有具有通过衬底上的钝化层暴露的第一和第二接触焊盘的衬底。 第一个冶金层在衬底上。 第二冶金层在第一冶金层之上。 保护层在第一接触垫上。

公开(公告)号：US07005370B2

公开(公告)日：2006-02-28

申请号：US10846176

申请日：2004-05-13

Applicant: Lun Zhao ,  Wan Lay Looi ,  Kyaw Oo Aung ,  Yonggang Jin ,  Jae-Yong Song ,  Won Sun Shin

Inventor： Lun Zhao ,  Wan Lay Looi ,  Kyaw Oo Aung ,  Yonggang Jin ,  Jae-Yong Song ,  Won Sun Shin

IPC: H01L21/441

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for manufacturing an integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is formed over the substrate. A second metallurgy layer is formed over the first metallurgy layer. The first metallurgy layer is removed while leaving a portion thereof over the second contact pad. The second metallurgy layer is removed while leaving a portion thereof over the second contact pad. A protective layer is formed over the first contact pad while removing the first metallurgy layer.

Abstract translation: 一种用于制造集成电路封装的方法设置有具有通过衬底上的钝化层暴露的第一和第二接触焊盘的衬底。 在衬底上形成第一冶金层。 在第一冶金层上形成第二冶金层。 第一冶金层被去除，同时将其一部分留在第二接触垫上。 除去第二冶金层，同时将其第一部分留在第二接触垫上。 在移除第一冶金层的同时在第一接触垫上方形成保护层。

公开(公告)号：US09013037B2

公开(公告)日：2015-04-21

申请号：US13232780

申请日：2011-09-14

Applicant: Yonggang Jin

Inventor： Yonggang Jin

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0384 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2784 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00

Abstract: A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars.

Abstract translation: 形成在半导体衬底上的倒装芯片结构包括位于半导体衬底的前表面上的多个接触焊盘的直接与电接触的第一多个铜柱。 一层模塑料定位在基材的正面上，围绕并包围第一多个柱中的每一个并且具有与每个铜柱的前表面共面的前表面。 第二多个铜柱中的每一个位于第一多个铜柱之一的前表面上，并且焊料凸块位于每个第二多个柱的正面上。

公开(公告)号：US08617987B2

公开(公告)日：2013-12-31

申请号：US12982697

申请日：2010-12-30

Applicant: Kah Wee Gan ,  Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

Inventor： Kah Wee Gan ,  Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  Y10T29/413 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

Abstract translation: 嵌入式晶片级球栅阵列（eWLB）通过将半导体管芯嵌入到模塑料中而形成。 在激光钻头的模塑料中形成沟槽。 第一层铜通过物理气相沉积沉积在沟槽的侧壁上。 然后通过无电解方法在第一层铜上形成第二层铜层。 然后通过电镀在第二层上形成第三层铜层。

公开(公告)号：US20120171875A1

公开(公告)日：2012-07-05

申请号：US12982707

申请日：2010-12-30

Applicant: Kah Wee Gan ,  Yonggang Jin

Inventor： Kah Wee Gan ,  Yonggang Jin

IPC: H01L21/324 ,  F27D3/00

CPC classification number: H01L21/67288

Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.

Abstract translation: 一种减少半导体晶片翘曲的系统和方法。 该系统包括用于将半导体晶片固定在加热区域中的装置。 该装置包括用于固定半导体晶片的边缘的保持机构。 该装置还包括减压装置，其降低半导体器件下方的压力，这进一步将半导体器件固定在加热区域中。 加热区域包括多个加热和冷却区域，其中半导体晶片经受各种温度。

公开(公告)号：US20120168943A1

公开(公告)日：2012-07-05

申请号：US12982719

申请日：2010-12-30

Applicant: Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

Inventor： Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

IPC: H01L23/485 ,  H01L21/50

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014

Abstract: A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package.

Abstract translation: 描述了半导体封装及其形成方法。 半导体封装由从具有钝化层的半导体晶片切割的半导体管芯形成。 将半导体晶片暴露于电离气体，导致钝化层变粗糙。 切割半导体晶片以形成多个具有粗糙化钝化层的半导体管芯。 多个半导体管芯被放置在粘合剂层上以形成重构的晶片，并且形成包封粘合剂层和多个半导体管芯的封装层。 去除钝化层，形成的半导体封装包括用于在半导体封装外部建立电连接的电触头。

公开(公告)号：US20120161319A1

公开(公告)日：2012-06-28

申请号：US12978144

申请日：2010-12-23

Applicant: Yaohuang Huang ,  Yonggang Jin ,  Puay Gek Chua ,  How Yuan Hwang

Inventor： Yaohuang Huang ,  Yonggang Jin ,  Puay Gek Chua ,  How Yuan Hwang

IPC: H01L21/02 ,  H01L23/482

CPC classification number: H01L24/03 ,  H01L23/53238 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing.

Abstract translation: 制造集成电路，晶片级集成电​​路封装或嵌入晶片级封装的工艺包括在衬底或子结构上形成铜接触焊盘。 子结构可以包括装置，并且接触垫可以用于形成到装置的电耦合。 例如，可以将铜电镀施加到子结构上，并且蚀刻铜电镀以在子结构上形成铜接触焊盘。 可以应用蚀刻工艺以去除子结构上的阻挡层材料，例如邻近铜焊盘。 例如，可以施加过氧化氢蚀刻以从底层结构的表面去除钛 - 钨。 再次蚀刻焊盘以从焊盘去除阻挡层蚀刻剂，副产物和/或氧化物。 可以执行污染控制步骤，例如快速冲洗和冲洗（QDR）和旋转冲洗干燥（SRD）处理。