Invention Grant
- Patent Title: Impedance compensated electrostatic discharge circuit for protection of high-speed interfaces and method of using the same
- Patent Title (中): 用于保护高速接口的阻抗补偿静电放电电路及其使用方法
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Application No.: US12332159Application Date: 2008-12-10
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Publication No.: US08351170B2Publication Date: 2013-01-08
- Inventor: Jeffrey C. Dunnihoo , Richard Kimoto
- Applicant: Jeffrey C. Dunnihoo , Richard Kimoto
- Applicant Address: US AZ Phoenix
- Assignee: Semiconductor Components Industries, LLC
- Current Assignee: Semiconductor Components Industries, LLC
- Current Assignee Address: US AZ Phoenix
- Main IPC: H02H9/00
- IPC: H02H9/00
Abstract:
The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.
Public/Granted literature
- US20090154038A1 IMPEDANCE COMPENSATED ESD CIRCUIT FOR PROTECTION FOR HIGH-SPEED INTERFACES AND METHOD OF USING THE SAME Public/Granted day:2009-06-18
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