Invention Grant
- Patent Title: Emulation of power shutoff behavior for integrated circuits
- Patent Title (中): 集成电路功率关断行为的仿真
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Application No.: US11966602Application Date: 2007-12-28
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Publication No.: US08352235B1Publication Date: 2013-01-08
- Inventor: Tsair-Chin Lin , Bing Zhu , Platon Beletsky
- Applicant: Tsair-Chin Lin , Bing Zhu , Platon Beletsky
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06G7/54
- IPC: G06G7/54 ; G06F17/50 ; G06F9/455

Abstract:
A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.
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