Provided is a transmission gate capable of adapting to various input voltages to attain high S/N characteristics. The transmission gate includes: a PMOS transistor (11) which includes a drain to which an input voltage (Vin) is input, is turned ON when a voltage (Vin−Vs1) is input to a gate thereof, and includes a source from which the input voltage (Vin) is output as an output voltage (Vout); and an NMOS transistor (12) which has a gate length, a gate width, a gate oxide thickness, and an absolute value of a threshold voltage which are the same as those of the PMOS transistor (11), includes a drain to which the input voltage (Vin) is input, is turned ON when a voltage (Vin+Vs1) is input to a gate thereof, and includes a source from which the input voltage (Vin) is output as the output voltage (Vout).