A phase locked loop (PLL) circuit includes a first signal detector having a first input terminal configured to receive a varying first input signal, a second input terminal configured to receive a feedback signal that corresponds to the center of the input frequency, and an output terminal configured to provide an output signal corresponding to a phase difference between the first input and feedback signals. A delay estimator has an input terminal configured to receive the output signal from the first phase detector and in response thereto, output a phase difference estimation signal. A variable delay circuit has an input terminal configured to receive the phase difference estimation signal and in response thereto, phase shift the second input signal.