Invention Grant
US08358165B2 Ultra-low voltage level shifting circuit 有权
超低电压电平移位电路

Ultra-low voltage level shifting circuit
Abstract:
A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL.
Public/Granted literature
Information query
Patent Agency Ranking
0/0