发明授权
US08359490B2 Memory controller, system including the controller, and memory delay amount control method
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存储器控制器，包括控制器的系统和存储器延迟量控制方法
- 专利标题： Memory controller, system including the controller, and memory delay amount control method
- 专利标题（中）： 存储器控制器，包括控制器的系统和存储器延迟量控制方法
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申请号： US13462689申请日： 2012-05-02
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公开(公告)号： US08359490B2公开(公告)日： 2013-01-22
- 发明人: Hideo Mochizuki , Kazuaki Masuda
- 申请人： Hideo Mochizuki , Kazuaki Masuda
- 申请人地址： JP Kawasaki-shi, Kanagawa
- 专利权人： Renesas Electronics Corporation
- 当前专利权人： Renesas Electronics Corporation
- 当前专利权人地址： JP Kawasaki-shi, Kanagawa
- 代理机构： McGinn IP Law Group, PLLC
- 优先权： JP2008-133698 20080521
- 主分类号： G06F1/12
- IPC分类号： G06F1/12
摘要：
A memory controller coupled to a DRAM includes a delay control section including a delay holding section, and coupled to the DRAM to output a delay set value to the DRAM and a delay adjustment section coupled to the DRAM to receive data from the DRAM, and to arrange a delay amount of the received data based on the delay set value. The delay set value is stored in both the delay holding section of the memory controller and the DRAM.
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