发明授权
- 专利标题: Method and mechanism for implementing extraction for an integrated circuit design
- 专利标题(中): 实现集成电路设计提取的方法和机制
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申请号: US12987064申请日: 2011-01-07
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公开(公告)号: US08375342B1公开(公告)日: 2013-02-12
- 发明人: Eric Nequist , Richard Brashears , Matthew A. Liberty , Michael C. McSherry
- 申请人: Eric Nequist , Richard Brashears , Matthew A. Liberty , Michael C. McSherry
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Vista IP Law Group, LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.
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