公开(公告)号：US08316331B1

公开(公告)日：2012-11-20

申请号：US12987072

申请日：2011-01-07

申请人： Eric Nequist ,  Richard Brashears ,  Matthew A. Liberty ,  Michael C. McSherry

发明人： Eric Nequist ,  Richard Brashears ,  Matthew A. Liberty ,  Michael C. McSherry

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： An improved method and system for stitching one or more islands of an integrated circuit design is disclosed. Multiple connected island objects in the IC design are first identified. At least one of the multiple identified connected island objects is then modified to form a modified island object. The modified island object may then be stitched into the multiple identified connected island objects. In some embodiments, stitching a modified island object may be implemented by tracking the endpoint(s), port(s), or node(s) of the connected island object being modified and stitched.

摘要翻译： 公开了一种用于拼接集成电路设计的一个或多个岛的改进的方法和系统。 首先确定IC设计中的多个连接岛对象。 然后修改多个确定的连接的岛对象中的至少一个以形成修改的岛对象。 然后可以将经修改的岛屿物体缝合到多个识别的连接的岛屿物体中。 在一些实施例中，缝合修改的岛屿对象可以通过跟踪被修改和缝合的连接的岛对象的端点，端口或节点来实现。

公开(公告)号：US20110314432A1

公开(公告)日：2011-12-22

申请号：US13221822

申请日：2011-08-30

申请人： David Cross ,  Eric Nequist

发明人： David Cross ,  Eric Nequist

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

摘要翻译： 公开了一种用于实现用于执行电子设计自动化（EDA）工具（诸如布局处理工具）的并行性的改进的方法和系统。 EDA布局处理工具的示例是放置和布线工具。 描述了有效的锁定机构，以便于并行处理并使阻塞最小化。

公开(公告)号：US07657860B1

公开(公告)日：2010-02-02

申请号：US11741694

申请日：2007-04-27

申请人： Richard Brashears ,  Eric Nequist

发明人： Richard Brashears ,  Eric Nequist

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.

摘要翻译： 公开了一种用于实现电路和芯片设计的路由的改进的方法，系统和制造。 路由架构可以表示为不同粒度路由级别的频谱。 代替基于区域的路由，可以针对特定路由或路由的一部分来执行路由。 路由的不同类型的抽象或抽象级别可以用于相同的网络或路由。 可以对集成电路设计的一部分进行部分拓扑重构，细化或分解，其中该部分小于整个路线或网络。 不一致的路由活动或资源级别可能被应用于路由设计。 可以使用优先级来设计具有比设计的其他部分更多的细节，抽象或资源的特定部分。

公开(公告)号：US20090172623A1

公开(公告)日：2009-07-02

申请号：US11964681

申请日：2007-12-26

申请人： David Cross ,  Eric Nequist

发明人： David Cross ,  Eric Nequist

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

摘要翻译： 公开了一种用于实现用于执行电子设计自动化（EDA）工具（诸如布局处理工具）的并行性的改进的方法和系统。 EDA布局处理工具的示例是放置和布线工具。 描述了有效的锁定机制，以便于并行处理并最小化阻塞。

公开(公告)号：US07461359B1

公开(公告)日：2008-12-02

申请号：US11229344

申请日：2005-09-15

申请人： Eric Nequist

发明人： Eric Nequist

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of identifying connected objects for a specific object. Instead of unfolding the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes need to be unfolded to perform the search.

摘要翻译： 公开了用于在电气设计中识别连接的形状和物体的方法和机构。 整个层次结构设计不需要被平坦化来执行识别特定对象的连接对象的操作。 而不是展开整个设计层次结构，只有落在形状几何范围内的形状的特定实例需要展开才能执行搜索。

公开(公告)号：US07100129B1

公开(公告)日：2006-08-29

申请号：US10342862

申请日：2003-01-14

申请人： Jeffrey Scott Salowe ,  Eric Nequist

发明人： Jeffrey Scott Salowe ,  Eric Nequist

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangle.

摘要翻译： 分析电子电路的设计的方法包括将设计细分为矩形网格，选择至少一个矩形作为第一级父矩形，以及基于第一级父矩形生成多个第二级子矩形。

公开(公告)号：US08136060B1

公开(公告)日：2012-03-13

申请号：US12648843

申请日：2009-12-29

申请人： Eric Nequist

发明人： Eric Nequist

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045 ,  G06F17/5081 ,  G06F17/509

摘要： A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

摘要翻译： 公开了用于在电气设计中识别和跟踪网络的方法和机构。 层次化设计不需要被平坦化，以执行识别和跟踪网络的操作。 为了识别连接形状的集合，而不是必须展开整个设计层次结构，只有落在被识别为网络一部分的形状的几何界限内的特定形状实例需要展开才能执行搜索。 当组合层次设计的网络列表时，可以基于虚拟终端结构来导出设计的其他层次级别的展开形状，这些虚拟终端结构隐含地引用其他级别的网络和对象。

公开(公告)号：US07971173B1

公开(公告)日：2011-06-28

申请号：US11741685

申请日：2007-04-27

申请人： Richard Brashears ,  Eric Nequist

发明人： Richard Brashears ,  Eric Nequist

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.

摘要翻译： 公开了一种用于实现电路和芯片设计的路由的改进的方法，系统和制造。 路由架构可以表示为不同粒度路由级别的频谱。 代替基于区域的路由，可以针对特定路由或路由的一部分来执行路由。 路由的不同类型的抽象或抽象级别可以用于相同的网络或路由。 可以对集成电路设计的一部分进行部分拓扑重构，细化或分解，其中该部分小于整个路线或网络。 不一致的路由活动或资源级别可能被应用于路由设计。 可以使用优先级来设计具有比设计的其他部分更多的细节，抽象或资源的特定部分。

公开(公告)号：US20110093826A1

公开(公告)日：2011-04-21

申请号：US12979064

申请日：2010-12-27

申请人： David WHITE ,  Eric NEQUIST

发明人： David WHITE ,  Eric NEQUIST

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5072

摘要： Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.

摘要翻译： 公开了一种用于实现基于模型的布局规划，布局，布置和路由的方法，系统和计算机程序产品。 基于制造变化的预测，模型用于指导IC布局上的多边形的放置和布线。

公开(公告)号：US07904862B2

公开(公告)日：2011-03-08

申请号：US11964676

申请日：2007-12-26

申请人： Eric Nequist

发明人： Eric Nequist

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects.

摘要翻译： 公开了一种用于在IC设计中识别基于间隔和间隙的规则违规的方法和机构。 使用阴影来识别基于间隔和间隙的规则违规。 阴影方法特别有助于识别宽度相关的间隔和间隙违规，同时避免存在替代方法的假阳性。 实施例可以与布局对象的任何类型，配置或形状一起使用。