Invention Grant
- Patent Title: Integrated circuit package system employing an offset stacked configuration and method for manufacturing thereof
- Patent Title (中): 采用偏移堆叠结构的集成电路封装系统及其制造方法
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Application No.: US12974265Application Date: 2010-12-21
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Publication No.: US08383458B2Publication Date: 2013-02-26
- Inventor: DaeSik Choi , BumJoon Hong , Sang-Ho Lee , Jong-Woo Ha , Soo-San Park
- Applicant: DaeSik Choi , BumJoon Hong , Sang-Ho Lee , Jong-Woo Ha , Soo-San Park
- Applicant Address: SG Singapore
- Assignee: Stats Chippac Ltd.
- Current Assignee: Stats Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Agent Mikio Ishimaru
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/02

Abstract:
A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect.
Public/Granted literature
Information query
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