公开(公告)号：US09299644B1

公开(公告)日：2016-03-29

申请号：US14285601

申请日：2014-05-22

申请人： Byung Tai Do ,  Arnel Trasporto ,  Zigmund Ramirez Camacho

发明人： Byung Tai Do ,  Arnel Trasporto ,  Zigmund Ramirez Camacho

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有凹部的具有顶部的端子; 在所述凹陷中施加电介质材料，所述电介质材料在其中形成间隙并暴露所述顶部的一部分; 在所述间隙内形成迹线并与所述顶部直接接触，所述迹线在所述电介质材料的上表面上横向延伸; 并通过轨迹将集成电路连接到终端。

公开(公告)号：US09280825B2

公开(公告)日：2016-03-08

申请号：US14202677

申请日：2014-03-10

申请人： Sony Corporation

发明人： Albert Huang ,  Ming-Chang Liu

IPC分类号： G06K9/00 ,  G06T7/00

CPC分类号： G06T7/0042 ,  G06F19/00 ,  G06T3/0068 ,  G06T7/33 ,  G06T7/73 ,  G06T19/006 ,  G06T2200/04 ,  G06T2207/10028 ,  G06T2210/41 ,  G16H40/63

摘要： An image processing system, and a method of operation thereof, including: a feature selection module for determining subsets of point clouds, the subsets selected based on key points of a three-dimensional object; a feature matching module, coupled to the feature selection module, for generating matched results based on a matching transformation of the subsets; and a point registration module, coupled to the feature matching module, for refining the matched results based on a refinement transformation to optionally align different data sets of the point clouds for displaying the aligned data sets on a device, wherein the refinement transformation includes a refinement error less than a matching error of the matching transformation.

摘要翻译： 一种图像处理系统及其操作方法，包括：用于确定点云的子集的特征选择模块，基于三维对象的关键点选择的子集; 特征匹配模块，耦合到所述特征选择模块，用于基于所述子集的匹配变换来生成匹配结果; 以及耦合到所述特征匹配模块的点注册模块，用于基于细化变换来精简所匹配的结果，以可选地对准所述点云的不同数据集，以在装置上显示对齐的数据集，其中所述细化变换包括细化 误差小于匹配变换的匹配误差。

公开(公告)号：US09257384B2

公开(公告)日：2016-02-09

申请号：US13488812

申请日：2012-06-05

申请人： Soohan Park ,  Sung Jun Yoon

发明人： Soohan Park ,  Sung Jun Yoon

IPC分类号： H01L29/66 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/49833 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/15311 ,  H01L21/78 ,  H01L2924/00

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch.

摘要翻译： 一种制造集成电路封装系统的方法，包括：提供基底; 将基板上的堆叠基板直接安装在基板与基板之间，基板间连接器具有基板间连接器间距; 将集成电路安装在所述堆叠衬底上，所述集成电路具有直接在所述堆叠衬底上的内部连接器; 并且将外部连接器直接连接到基底基板上，该外部连接器具有大于基板间连接器间距的外部连接器间距。

公开(公告)号：US09235903B2

公开(公告)日：2016-01-12

申请号：US14244470

申请日：2014-04-03

申请人： Sony Corporation

发明人： Bi Song ,  Ming-Chang Liu

IPC分类号： G06K9/34 ,  G06K9/36 ,  G06T7/00 ,  G06T11/60

CPC分类号： G06T7/0081 ,  G06K9/34 ,  G06T7/0012 ,  G06T7/11 ,  G06T7/12 ,  G06T7/136 ,  G06T11/60 ,  G06T2207/10016 ,  G06T2207/10048 ,  G06T2207/10088 ,  G06T2207/10104 ,  G06T2207/10116 ,  G06T2207/10132 ,  G06T2207/20072 ,  G06T2207/20152

摘要： An image processing system and method of operation includes: a source image having source pixels; a homogeneity image module for forming a homogeneity image having homogeneity pixels each with a homogeneity value indicating the local homogeneity of source pixels of the source image; a watershed image module, coupled to the homogeneity image module, for forming a watershed image having watershed segments with a segment weight, the watershed image formed by segmenting the homogeneity image, and for merging one of the watershed segments with another of the watershed segments both having the segment weight less than or equal to a segment threshold; a contour map module, coupled to the watershed image module, for forming a segmentation contour map having boundaries of the watershed segments formed by merging the watershed segments; and a composite image module for forming a composite image with the segmentation contour map for display on a device.

摘要翻译： 一种图像处理系统和操作方法，包括：具有源像素的源图像; 均匀性图像模块，用于形成具有均匀性像素的均匀性图像，每个像素均具有指示源图像的源像素的局部均匀性的均匀性值; 耦合到均匀性图像模块的分水岭图像模块，用于形成具有分段权重的分水岭图像的分水岭图像，通过分割均匀图像形成的分水岭图像，以及用于将一个分水岭段与另一个分水岭段合并 具有小于或等于段阈值的段权重; 耦合到分水岭图像模块的轮廓图模块，用于形成具有通过合并流水段而形成的分水岭段的边界的分割等值线图; 以及用于形成具有用于在设备上显示的分割等值线图的合成图像的合成图像模块。

公开(公告)号：US09202777B2

公开(公告)日：2015-12-01

申请号：US12131037

申请日：2008-05-30

申请人： Lionel Chien Hui Tay ,  Seng Guan Chow ,  Zigmund Ramirez Camacho

发明人： Lionel Chien Hui Tay ,  Seng Guan Chow ,  Zigmund Ramirez Camacho

IPC分类号： H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package system includes: providing a leadframe having inner frame bars, outer frame bars, a die pad, tiebars, and rows of leads, the inner frame bars being coplanar with outer frame bars; attaching a semiconductor chip to the die pad; attaching bond wires between the semiconductor chip and the rows of leads; encapsulating the semiconductor chip, the bond wires, the inner frame bars, the outer frame bars, the die pad, the tiebars, and the rows of leads in an encapsulant; cutting a groove to remove the inner frame bars; and singulating the leadframe and the encapsulant to remove the outer frame bars.

摘要翻译： 半导体封装系统包括：提供具有内框架条，外框架条，管芯焊盘，拉杆和一排引线的引线框架，内框架杆与外框架杆共面; 将半导体芯片附接到芯片焊盘; 在半导体芯片和引线列之间附加接合线; 在封装材料中封装半导体芯片，接合线，内框架条，外框架条，管芯焊盘，拉杆和引线列; 切割凹槽以移除内框架条; 并且分离引线框和密封剂以去除外框架条。

公开(公告)号：US09202776B2

公开(公告)日：2015-12-01

申请号：US11754603

申请日：2007-05-29

申请人： Jae Hak Yee

发明人： Jae Hak Yee

IPC分类号： H01L23/02 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/552

CPC分类号： H01L23/49537 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49575 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/731 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stackable multi-chip package system is provided including forming an inter-chip structure adjacent to an external interconnect having both a base and a tip; connecting a first integrated circuit die and an outer portion of the base with the first integrated circuit die mounted over the inter-chip structure, connecting a second integrated circuit die and an inner portion of the base with the second integrated circuit die mounted under the inter-chip structure, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed.

摘要翻译： 提供了一种可堆叠的多芯片封装系统，包括与具有基极和尖端的外部互连相邻形成芯片间结构; 将第一集成电路管芯和基座的外部部分与安装在芯片间结构上的第一集成电路管芯连接，将第二集成电路管芯和基部的内部部分连接到安装在管脚下方的第二集成电路管芯 芯片结构，并且模制第一集成电路管芯，第二集成电路管芯和外部互连部分露出。

公开(公告)号：US09171795B2

公开(公告)日：2015-10-27

申请号：US14556992

申请日：2014-12-01

申请人： Dong Ju Jeon ,  KyoungHee Park ,  YoungDal Roh ,  JinHee Jung

发明人： Dong Ju Jeon ,  KyoungHee Park ,  YoungDal Roh ,  JinHee Jung

IPC分类号： H01L21/4763 ,  H01L23/04 ,  H05K1/18 ,  H01L23/498 ,  H01L21/52 ,  H01L21/48 ,  H01L21/768 ,  H01L23/538 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L23/49861 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4821 ,  H01L21/486 ,  H01L21/52 ,  H01L21/76804 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, including: an embedding material on a component; a mask layer on the embedding material; a buried pattern in the mask layer, the outer surface of the buried pattern coplanar with the outer surface of the mask layer, the buried pattern electrically connected to the component; a patterned dielectric on a portion of the buried pattern; and an integrated circuit die on the buried pattern.

摘要翻译： 一种集成电路封装系统及其集成电路封装系统的制造方法，包括：嵌入材料在部件上; 嵌入材料上的掩模层; 掩模图案中的掩埋图案，掩模图案的外表面与掩模层的外表面共面，埋入图案电连接到部件; 在掩埋图案的一部分上的图案化电介质; 并在埋藏图案上集成电路裸片。

公开(公告)号：US09171739B1

公开(公告)日：2015-10-27

申请号：US14313452

申请日：2014-06-24

申请人： YoungDal Roh ,  DeokKyung Yang ,  HeeSoo Lee

发明人： YoungDal Roh ,  DeokKyung Yang ,  HeeSoo Lee

IPC分类号： H01L23/28 ,  H01L21/44 ,  H01L21/48 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L21/486 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16014 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2924/14 ,  H01L2924/15311

摘要： An integrated circuit packaging system, and a method of manufacture thereof, including: a patterned first conductive plating; a molding on the patterned first conductive plating; a through via through the molding; a second conductive plating on the molding and the through via; a protection layer partially covering the first conductive plating, the second conductive plating and the molding; a device on the first conductive plating; and an external connector being attached to the second conductive plating.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：图案化的第一导电电镀; 在图案化的第一导电电镀上的模制品; 通过成型的通孔; 在模制件和通孔上的第二导电电镀; 部分地覆盖第一导电镀层，第二导电镀层和模制件的保护层; 第一导电电镀装置; 以及连接到第二导电电镀层的外部连接器。

公开(公告)号：US09147662B1

公开(公告)日：2015-09-29

申请号：US14137755

申请日：2013-12-20

申请人： Byung Tai Do ,  Arnel Senosa Trasporto ,  Sung Soo Kim

发明人： Byung Tai Do ,  Arnel Senosa Trasporto ,  Sung Soo Kim

IPC分类号： H01L23/492 ,  H01L23/00

CPC分类号： H01L21/4857 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit packaging system including: a fiber-less organic substrate including: a first dielectric layer, a first metal layer on the first dielectric layer, a second dielectric layer on the first dielectric layer and the first metal layer, and an interconnect via plated on the first metal layer and the second dielectric layer; an integrated circuit mounted over the second dielectric layer; and an integrated circuit interconnect between the integrated circuit and the interconnect via.

摘要翻译： 一种集成电路封装系统，包括：无纤维有机基底，包括：第一介电层，第一介电层上的第一金属层，第一介电层和第一金属层上的第二介电层，以及经电镀的互连 在第一金属层和第二介电层上; 安装在所述第二电介质层上的集成电路; 以及集成电路和互连通孔之间的集成电路互连。

公开(公告)号：US09129978B1

公开(公告)日：2015-09-08

申请号：US14313521

申请日：2014-06-24

申请人： Jaepil Kim ,  Seokhyun Kim ,  Daeup Bae ,  Jaewon Kim ,  Jaekang Yoo ,  Sungpil Hur

发明人： Jaepil Kim ,  Seokhyun Kim ,  Daeup Bae ,  Jaewon Kim ,  Jaekang Yoo ,  Sungpil Hur

IPC分类号： H01L23/48 ,  H01L23/28 ,  H01L21/44 ,  H01L21/56

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

摘要： An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, includes: a singulation substrate having an air vent portion having longitudinal grooves in the air vent portion, the longitudinal grooves all parallel to each other; an integrated circuit die attached to the singulation substrate; and a molding compound on the singulation substrate, on the air vent portion, in a portion of the longitudinal grooves, and on the integrated circuit die.

摘要翻译： 一种集成电路封装系统及其集成电路封装系统的制造方法，其特征在于，包括：排气基板，其具有在所述排气部中具有纵向槽的排气部，所述纵向槽全部平行; 附接到单片基板的集成电路芯片; 在分离基板上，排气部分，纵向槽的一部分和集成电路管芯上的模塑料。