- 专利标题： Pattern verifying method, pattern verifying device, program, and manufacturing method of semiconductor device
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申请号： US12457105申请日： 2009-06-01
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公开(公告)号： US08397182B2公开(公告)日： 2013-03-12
- 发明人: Seiji Nagahara
- 申请人： Seiji Nagahara
- 申请人地址： JP Kawasaki-Shi, Kanagawa
- 专利权人： Renesas Electronics Corporation
- 当前专利权人： Renesas Electronics Corporation
- 当前专利权人地址： JP Kawasaki-Shi, Kanagawa
- 代理机构： McGinn IP Law Group, PLLC
- 优先权： JP2008-145681 20080603
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
An overlapping margin of a second pattern for a first pattern is corrected for at least one of the first pattern and the second pattern (S50). Next, a relative distance between the first pattern and the second pattern after the overlapping margin is corrected is calculated (S60). Next, it is determined whether or not the relative distance satisfies a criterion (S70). Thus, the pattern can be verified under the consideration of the overlapping margin.
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