Invention Grant
US08399282B2 Method for forming pad in wafer with three-dimensional stacking structure
有权
在具有三维堆叠结构的晶片中形成焊盘的方法
- Patent Title: Method for forming pad in wafer with three-dimensional stacking structure
- Patent Title (中): 在具有三维堆叠结构的晶片中形成焊盘的方法
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Application No.: US13026963Application Date: 2011-02-14
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Publication No.: US08399282B2Publication Date: 2013-03-19
- Inventor: Heui Gyun Ahn , Se Jung Oh , In Gyun Jeon , Jun Ho Won
- Applicant: Heui Gyun Ahn , Se Jung Oh , In Gyun Jeon , Jun Ho Won
- Applicant Address: KR Seoul
- Assignee: Siliconfile Technologies Inc.
- Current Assignee: Siliconfile Technologies Inc.
- Current Assignee Address: KR Seoul
- Agency: Kile Park Goekjian Reed & McManus PLLC
- Priority: KR10-2010-0015632 20100222
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, forming vias that pass through the anti-reflective layer and the back side dielectric layer and contact back sides of super contacts which are formed on the Si substrate, and forming a pad on the back side dielectric layer such that the pad is electrically connected to the vias.
Public/Granted literature
- US20110207258A1 METHOD FOR FORMING PAD IN WAFER WITH THREE-DIMENSIONAL STACKING STRUCTURE Public/Granted day:2011-08-25
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