Invention Grant
- Patent Title: Capping before barrier-removal IC fabrication method
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Application No.: US13270809Application Date: 2011-10-11
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Publication No.: US08415261B1Publication Date: 2013-04-09
- Inventor: Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
- Applicant: Jonathan D. Reid , Eric G. Webb , Edmund B. Minshall , Avishai Kepten , R. Marshall Stowell , Steven T. Mayer
- Applicant Address: US CA Fremont
- Assignee: Novellus Systems, Inc.
- Current Assignee: Novellus Systems, Inc.
- Current Assignee Address: US CA Fremont
- Agency: Weaver Austin Villeneuve & Sampson LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; B01J19/12

Abstract:
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
Information query
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