Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.