公开(公告)号：US20130086545A1

公开(公告)日：2013-04-04

申请号：US13252868

申请日：2011-10-04

申请人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

摘要翻译： 集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％ 和20％。 水平和垂直的全局边缘分开处理。 可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。 可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。 直方图还可以与拥塞驱动的物理综合工具结合使用。

公开(公告)号：US08584070B2

公开(公告)日：2013-11-12

申请号：US13252868

申请日：2011-10-04

申请人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Lakshmi N. Reddy ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools.

摘要翻译： 集成电路设计中的全局路由拥塞的特征在于计算全局边缘拥塞并构建全局边缘拥塞的平均值的直方图，用于不同百分比的最差边缘拥塞，例如0.5％，1％，2％，5％，10％ 和20％。 水平和垂直的全局边缘分开处理。 可以跳过阻塞附近的全局边缘，以避免虚假拥塞热点。 可将当前全局路由的直方图与先前全局路由的直方图进行比较，以选择最佳路由解决方案。 直方图还可以与拥塞驱动的物理综合工具结合使用。

公开(公告)号：US20130086544A1

公开(公告)日：2013-04-04

申请号：US13252067

申请日：2011-10-03

申请人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

摘要翻译： 通过考虑本地路由和引脚访问来增强全局路由和拥塞评估。 针对每个全局边缘基于相邻瓦片计算引脚信息，并且基于引脚信息减少边缘的布线轨迹容量。 在全局路由之后，为了详细路由，线路轨道容量会增加先前的减少量。 引脚信息可以包括相关瓦片的引脚数，引脚的Steiner树长度或引脚的相对位置。 优选地通过在用于针的逻辑门的电路设计的特定金属层的轨道中产生阻塞来减少接线轨迹容量。 阻塞轨道可以均匀地分布在给定边缘的接线轨道上。

公开(公告)号：US08418113B1

公开(公告)日：2013-04-09

申请号：US13252067

申请日：2011-10-03

申请人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles J. Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge.

摘要翻译： 通过考虑本地路由和引脚访问来增强全局路由和拥塞评估。 针对每个全局边缘基于相邻瓦片计算引脚信息，并且基于引脚信息减少边缘的布线轨迹容量。 在全局路由之后，为了详细路由，线路轨道容量会增加先前的减少量。 引脚信息可以包括相关瓦片的引脚数，引脚的Steiner树长度或引脚的相对位置。 优选地通过在用于针的逻辑门的电路设计的特定金属层的轨道中产生阻塞来减少接线轨迹容量。 阻塞轨道可以均匀地分布在给定边缘的接线轨道上。

公开(公告)号：US20140071827A1

公开(公告)日：2014-03-13

申请号：US13612392

申请日：2012-09-12

申请人： CHARLES JAY ALPERT ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： CHARLES JAY ALPERT ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： H04W28/10

CPC分类号： H04L47/125 ,  H04L45/22 ,  H04L45/28

摘要： A method, system, and computer program product for solving a network traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested network route section is selected from a set of congested network route sections. A set of congesting devices is selected, where the set of congesting devices causes congestion in the selected congested network route sections by using the selected congested network route section. A vacancy data structure corresponding to the selected congested network route section is populated. A subset of the set of the congesting devices is selected. The subset of the set of the congesting devices is rerouted to a candidate network route section identified in the vacancy data structure.

摘要翻译： 在说明性实施例中提供了用于解决网络交通拥塞问题的方法，系统和计算机程序产品。 使用在数据处理系统中使用处理器和存储器执行的应用，从一组拥塞的网络路由部分中选择拥塞的网络路由部分。 选择一组拥塞装置，其中，所述一组拥塞装置通过使用所选择的拥塞网络路由部分在所选择的拥塞网络路由部分中引起拥塞。 填充与所选择的拥塞网络路由部分相对应的空位数据结构。 选择一组拥塞装置的子集。 拥塞设备的集合的子集被重新路由到在空白数据结构中标识的候选网络路由部分。

公开(公告)号：US20140074389A1

公开(公告)日：2014-03-13

申请号：US13612331

申请日：2012-09-12

申请人： Charles Jay Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles Jay Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G08G1/00

CPC分类号： G08G9/00 ,  G08G1/0104

摘要： A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.

公开(公告)号：US20130272126A1

公开(公告)日：2013-10-17

申请号：US13445150

申请日：2012-04-12

申请人： Charles Jay Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles Jay Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： H04L12/24

CPC分类号： H04L41/145 ,  H04L45/125

摘要： In congestion aware point-to-point routing using a random point in an integrated circuit (IC) design, the random point is selected in a bounding area defined in a layout of the IC design. A set of pattern routes is constructed between a source pin and a sink pin in the bounding area, a pattern route in the set of pattern routes passing through the random point. A set of congestion cost corresponding to the set of pattern routes is computed. A congestion cost in the set of congestion costs corresponds to a pattern route in the set of pattern routes. A preferred pattern route is selected from the set of pattern routes, the preferred pattern route having the smallest congestion cost in the set of congestion costs. The preferred pattern route is output as a point-to-point route between the source pin and the sink pin.

摘要翻译： 在使用集成电路（IC）设计中的随机点的拥塞感知点对点路由中，随机点在IC设计的布局中定义的边界区域中选择。 在边界区域中的源极引脚和引脚引脚之间构成一组模式路由，即通过随机点的模式路由集合中的模式路由。 计算与该组模式路由相对应的一组拥塞成本。 该拥塞成本集中的拥塞成本对应于该组模式路由中的模式路由。 从一组模式路由中选择优选模式路由，优选模式路由在拥塞成本集合中具有最小拥塞成本。 优选的模式路由作为源引脚和引脚引脚之间的点到点路由输出。

公开(公告)号：US08831875B2

公开(公告)日：2014-09-09

申请号：US13612331

申请日：2012-09-12

申请人： Charles Jay Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles Jay Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G01C21/00 ,  G08G1/123

CPC分类号： G08G9/00 ,  G08G1/0104

摘要： A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.

摘要翻译： 在说明性实施例中提供了用于解决交通拥堵问题的方法，系统和计算机程序产品。 使用在数据处理系统中使用处理器和存储器执行的应用程序，从一组拥塞的路由部分中选择拥塞的路由部分。 选择一组拥堵车辆，其中，所述一组拥堵车辆通过定位在所选择的拥塞路线部分上而导致所选择的拥塞路线部分中的拥塞。 填充与所选择的拥塞路由部分对应的空位数据结构。 选择一组拥堵车辆的一部分。 拥挤车辆的集合的子集被重新路由到在空缺数据结构中标识的候选路线部分。

公开(公告)号：US08601425B2

公开(公告)日：2013-12-03

申请号：US13445128

申请日：2012-04-12

申请人： Charles Jay Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

发明人： Charles Jay Alpert ,  Zhuo Li ,  Chin Ngai Sze ,  Yaoguang Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method, system, and computer program product for solving a congestion problem in an integrated circuit (IC) design are provided in the illustrative embodiments. A congested g-edge is selected from a set of congested g-edges. A set of congesting nets is selected, wherein the set of congesting nets cause congestion in the selected congested g-edges by crossing the selected congested g-edge. A vacancy data structure corresponding to the selected congested g-edge is populated. A subset of the set of the congesting nets is selected. The subset of the set of the congesting nets is rerouted to a candidate g-edge identified in the vacancy data structure.

摘要翻译： 在说明性实施例中提供了用于解决集成电路（IC）设计中的拥塞问题的方法，系统和计算机程序产品。 从一组拥塞的g边缘中选择拥塞的g边。 选择一组拥塞网络，其中所述拥塞网络集合通过穿过所选择的拥塞的g边缘而导致所选择的拥塞的g边缘中的拥塞。 填充与所选择的拥塞的g边缘对应的空位数据结构。 选择一组拥塞网络的子集。 拥塞网络集合的子集被重新路由到在空白数据结构中标识的候选g边。

公开(公告)号：US20120124539A1

公开(公告)日：2012-05-17

申请号：US12947445

申请日：2010-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

摘要翻译： 提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。 物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。 物理综合工具克隆了第一个本地时钟缓冲区。 然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。 在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。 该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。 该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。 放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。