发明授权
- 专利标题： Load reduced memory module and memory system including the same
- 专利标题（中）： 负载减少的内存模块和包含相同的内存系统
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申请号： US12801326申请日： 2010-06-03
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公开(公告)号： US08422263B2公开(公告)日： 2013-04-16
- 发明人: Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
- 申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
- 申请人地址： JP Tokyo
- 专利权人： Elpida Memory, Inc.
- 当前专利权人： Elpida Memory, Inc.
- 当前专利权人地址： JP Tokyo
- 代理机构： McGinn IP Law Group, PLLC
- 优先权： JP2009-136649 20090605
- 主分类号： G11C5/06
- IPC分类号： G11C5/06
摘要：
A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
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