发明授权
US08426265B2 Method for growing strain-inducing materials in CMOS circuits in a gate first flow
有权
在栅极第一流中在CMOS电路中增长应变诱导材料的方法
- 专利标题: Method for growing strain-inducing materials in CMOS circuits in a gate first flow
- 专利标题(中): 在栅极第一流中在CMOS电路中增长应变诱导材料的方法
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申请号: US12938457申请日: 2010-11-03
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公开(公告)号: US08426265B2公开(公告)日: 2013-04-23
- 发明人: Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
- 申请人: Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
- 申请人地址: US NY Armonk KY Grand Cayman
- 专利权人: International Business Machines Corporation,GlobalFoundries, Inc.
- 当前专利权人: International Business Machines Corporation,GlobalFoundries, Inc.
- 当前专利权人地址: US NY Armonk KY Grand Cayman
- 代理机构: Gibb & Riley, LLC
- 代理商 Yuanmin Cai, Esq.
- 主分类号: H01L21/8238
- IPC分类号: H01L21/8238
摘要:
A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.