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    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
    1.
    发明申请
    METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
    在门电路第一流程中生长应变诱导材料的方法

    公开(公告)号：US20120104507A1

    公开(公告)日：2012-05-03

    申请号：US12938457

    申请日：2010-11-03

    申请人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    发明人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823828

    摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

    摘要翻译： 一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于 厚度减小 在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

    Method for growing strain-inducing materials in CMOS circuits in a gate first flow
    2.
    发明授权
    Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
    在栅极第一流中在CMOS电路中增长应变诱导材料的方法

    公开(公告)号：US08426265B2

    公开(公告)日：2013-04-23

    申请号：US12938457

    申请日：2010-11-03

    申请人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    发明人： Bo Bai ,  Linda Black ,  Abhishek Dube ,  Judson R. Holt ,  Viorel C. Ontalus ,  Kathryn T. Schonenberg ,  Matthew W. Stoker ,  Keith H. Tabakman

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823828

    摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

    摘要翻译： 一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于 厚度减小 在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

    METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING
    4.
    发明申请
    METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING 失效
    通过退火减少堆叠不良的方法

    公开(公告)号：US20100283089A1

    公开(公告)日：2010-11-11

    申请号：US12839588

    申请日：2010-07-20

    申请人： Yun-Yu Wang ,  Christopher D. Sheraw ,  Anthony G. Domenicucci ,  Linda Black ,  Judson R. Holt ,  David M. Fried

    发明人： Yun-Yu Wang ,  Christopher D. Sheraw ,  Anthony G. Domenicucci ,  Linda Black ,  Judson R. Holt ,  David M. Fried

    IPC分类号： H01L29/04

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

    摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

    摘要翻译： 因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。 根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。 在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。 然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

    Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof
    6.
    发明授权
    Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof 失效
    包括多个晶体取向的半导体结构及其制造方法

    公开(公告)号：US07494918B2

    公开(公告)日：2009-02-24

    申请号：US11538963

    申请日：2006-10-05

    申请人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

    发明人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

    IPC分类号： H01L21/4763 ,  H01L29/04

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

    摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

    摘要翻译： 半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。 半导体衬底暴露在绝缘体内半导体结构内的孔内。 外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。 半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。

    METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING
    7.
    发明申请
    METHOD OF REDUCING STACKING FAULTS THROUGH ANNEALING 有权
    通过退火减少堆叠不良的方法

    公开(公告)号：US20080087961A1

    公开(公告)日：2008-04-17

    申请号：US11548428

    申请日：2006-10-11

    申请人： Yun-Yu Wang ,  Christopher D. Sheraw ,  Anthony G. Domenicucci ,  Linda Black ,  Judson R. Holt ,  David M. Fried

    发明人： Yun-Yu Wang ,  Christopher D. Sheraw ,  Anthony G. Domenicucci ,  Linda Black ,  Judson R. Holt ,  David M. Fried

    IPC分类号： H01L27/092 ,  H01L21/8232

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

    摘要： Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

    摘要翻译： 因此，在本发明的一个实施例中，提供了一种用于减少外延半导体层中的堆垛层错的方法。 根据这种方法，提供了一种衬底，其包括包括第一半导体材料的第一单晶半导体区域，第一半导体区域具有<110>晶体取向。 在第一半导体区域上生长包括第一半导体材料的外延层，具有<110>晶体取向的外延层。 然后在包括氢气的环境中，在大于1100摄氏度的温度下将衬底与外延层退火，由此退火步骤减少外延层中的堆垛层错。

    SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND METHODS FOR FABRICATION THEREOF
    10.
    发明申请
    SEMICONDUCTOR STRUCTURES INCLUDING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND METHODS FOR FABRICATION THEREOF 失效
    包括多个晶体学方位的半导体结构及其制造方法

    公开(公告)号：US20080083952A1

    公开(公告)日：2008-04-10

    申请号：US11538963

    申请日：2006-10-05

    申请人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

    发明人： Byeong Y. Kim ,  Xiaomeng Chen ,  Judson R. Holt ,  Christopher D. Sheraw ,  Linda Black ,  Igor Peidous

    IPC分类号： H01L27/12 ,  H01L21/84

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

    摘要： Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.

    摘要翻译： 半导体结构及其制造方法基于外延表面半导体层在具有第一晶体取向的半导体衬底上外延生长。 半导体衬底暴露在绝缘体内半导体结构内的孔内。 外延表面半导体层与绝缘体半导体结构内的具有第二结晶取向的表面半导体层交替接触或隔离。 半导体表面层相对于其下方的掩埋介电层的凹部和其上的硬掩模层提供了外延表面半导体层内的抑制的第二结晶相生长。