Invention Grant
US08432721B2 Method of programming variable resistance element, method of initializing variable resistance element, and nonvolatile storage device
有权
编程可变电阻元件的方法,初始化可变电阻元件的方法和非易失性存储器件
- Patent Title: Method of programming variable resistance element, method of initializing variable resistance element, and nonvolatile storage device
- Patent Title (中): 编程可变电阻元件的方法,初始化可变电阻元件的方法和非易失性存储器件
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Application No.: US13201890Application Date: 2011-02-01
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Publication No.: US08432721B2Publication Date: 2013-04-30
- Inventor: Mitsuteru Iijima , Takeshi Takagi
- Applicant: Mitsuteru Iijima , Takeshi Takagi
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, LLP.
- Priority: JP2010-021661 20100202
- International Application: PCT/JP2011/000545 WO 20110201
- International Announcement: WO2011/096194 WO 20110811
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw1|>|Vw2|, Vw1 representing voltage of the writing pulse for first to N-th writing steps, and Vw2 representing voltage of the writing pulse for (N+1)-th and subsequent writing steps, N being at least equal to 1, te1>te2, te1 representing pulse width of the erasing pulse for first to M-th erasing steps, and te2 representing pulse width of the erasing pulse for (M+1)-th and subsequent erasing steps. M>1. The (N+1)-th writing step follows the M-th erasing step.
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