发明授权
- 专利标题: Metastability effects simulation for a circuit description
- 专利标题(中): 电路描述的均衡性效应模拟
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申请号: US12773462申请日: 2010-05-04
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公开(公告)号: US08438516B2公开(公告)日: 2013-05-07
- 发明人: Tai An Ly , Ka Kei Kwok , Vijaya Vardhan Gupta , Lawrence Curtis Widdoes, Jr.
- 申请人: Tai An Ly , Ka Kei Kwok , Vijaya Vardhan Gupta , Lawrence Curtis Widdoes, Jr.
- 申请人地址: US OR Wilsonville
- 专利权人: Mentor Graphics Corporation
- 当前专利权人: Mentor Graphics Corporation
- 当前专利权人地址: US OR Wilsonville
- 代理机构: Klarquist Sparkman, LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/455
摘要:
A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files.
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