Invention Grant
- Patent Title: Chip stacking structure
- Patent Title (中): 芯片堆叠结构
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Application No.: US13228549Application Date: 2011-09-09
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Publication No.: US08441134B2Publication Date: 2013-05-14
- Inventor: Chien-Li Kuo , Yung-Chang Lin , Ming-Tse Lin
- Applicant: Chien-Li Kuo , Yung-Chang Lin , Ming-Tse Lin
- Applicant Address: TW Hsinchu
- Assignee: United Microelectronics Corporation
- Current Assignee: United Microelectronics Corporation
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, PC
- Agent Justin King
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/48 ; H01L27/146 ; H01L27/148

Abstract:
A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.
Public/Granted literature
- US20130062780A1 CHIP STACKING STRUCTURE Public/Granted day:2013-03-14
Information query
IPC分类: