Invention Grant
- Patent Title: Quasi-vertical structure for high voltage MOS device
- Patent Title (中): 高电压MOS器件的准垂直结构
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Application No.: US12699397Application Date: 2010-02-03
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Publication No.: US08445955B2Publication Date: 2013-05-21
- Inventor: Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao Chin Tuan
- Applicant: Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Hsiao Chin Tuan
- Applicant Address: TW
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW
- Agency: Lowe Hauptman Ham & Berner, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/336

Abstract:
A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer.
Public/Granted literature
- US20100219463A1 QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE Public/Granted day:2010-09-02
Information query
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