发明授权
- 专利标题： 3D multiple die stacking
- 专利标题（中）： 3D多芯片堆叠
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申请号： US12561618申请日： 2009-09-17
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公开(公告)号： US08455270B2公开(公告)日： 2013-06-04
- 发明人: Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer
- 申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理商 Catherine Ivers; Ira D. Blecker
- 主分类号： G01R31/26
- IPC分类号： G01R31/26 ; H01L21/66
摘要：
A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.
公开/授权文献
- US20110065214A1 3D MULTIPLE DIE STACKING 公开/授权日：2011-03-17