发明授权
US08455356B2 Integrated void fill for through silicon via 有权
通过硅通孔的集成空隙填充

Integrated void fill for through silicon via
摘要:
A microelectronic assembly and related method of forming a through hole extending through a first wafer and a second wafer are provided. The first and second wafer have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers. A hole can be etched downwardly through the first wafer until a gap is partially exposed between the confronting faces of the first and second wafers. The hole can have a first wall extending in a vertical direction, and a second wall sloping inwardly from the first wall to an inner opening through which the interfacial gap is exposed. Material of the first or second wafers exposed within the hole can then be sputtered such that at least some of the sputtered material deposits onto at least one of the exposed confronting faces of the first and second wafers and provides a wall between the confronting faces. The method can include resuming etching the hole so as to extend the first wall fully through the first wafer, the wall between the wafers and into the second wafer, such that the wall of the hole extends continuously from the first wafer into the second wafer. An electrically conductive through silicon via can then be formed extending through the first wafer, the wall between the wafers and into the second wafer.
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