A flash memory cell stack includes a semiconductor substrate; a control electrode formed in a vertical pillar shape on a surface of the semiconductor substrate; an insulating film formed between the control electrode and the semiconductor substrate; a gate stack formed on a side surface of the control electrode; a plurality of first insulating films formed as layers on a side surface of the gate stack; a plurality of second doping semiconductor areas formed as layers on a side surface of the gate stack; and a first doping semiconductor area formed on a portion of side surfaces of the first insulating films and the second doping semiconductor areas and formed on side surfaces facing each other in a first direction. The first insulating films and the second doping semiconductor areas are alternately provided on the side surface of the gate stack.