Invention Grant
- Patent Title: Negative voltage level shifter circuit
- Patent Title (中): 负电压电平转换电路
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Application No.: US13172625Application Date: 2011-06-29
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Publication No.: US08461899B2Publication Date: 2013-06-11
- Inventor: Vikas Rana
- Applicant: Vikas Rana
- Applicant Address: NL Amsterdam
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Hogan Lovells US LLP
- Priority: IN85/DEL/2011 20110114
- Main IPC: H03L5/00
- IPC: H03L5/00

Abstract:
A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits.
Public/Granted literature
- US20120182060A1 NEGATIVE VOLTAGE LEVEL SHIFTER CIRCUIT Public/Granted day:2012-07-19
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