公开(公告)号：US08461899B2

公开(公告)日：2013-06-11

申请号：US13172625

申请日：2011-06-29

Applicant: Vikas Rana

Inventor： Vikas Rana

IPC: H03L5/00

CPC classification number: H03K3/356165

Abstract: A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits.

Abstract translation: 负电压电平移位器电路包括一对输入晶体管，每个输入晶体管的栅极由输入信号和输入信号的反相形式中的一个驱动，耦合到该对输入晶体管的共源共栅子电路，以及 一对交叉耦合晶体管，用于根据输入信号锁定电压电平移位器的状态，其中交叉耦合晶体管的各个栅极由各个比较器子电路的输出驱动。

公开(公告)号：US20110299355A1

公开(公告)日：2011-12-08

申请号：US12840660

申请日：2010-07-21

Applicant: Vikas Rana

Inventor： Vikas Rana

IPC: G11C8/08

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。

公开(公告)号：US20120182060A1

公开(公告)日：2012-07-19

申请号：US13172625

申请日：2011-06-29

Applicant: Vikas Rana

Inventor： Vikas Rana

IPC: H03L5/00

CPC classification number: H03K3/356165

Abstract: A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits.

Abstract translation: 负电压电平移位器电路包括一对输入晶体管，每个输入晶体管的栅极由输入信号和输入信号的反相形式中的一个驱动，耦合到该对输入晶体管的共源共栅子电路，以及 一对交叉耦合晶体管，用于根据输入信号锁定电压电平移位器的状态，其中交叉耦合晶体管的各个栅极由各个比较器子电路的输出驱动。

公开(公告)号：US08750049B2

公开(公告)日：2014-06-10

申请号：US12840660

申请日：2010-07-21

Applicant: Vikas Rana

Inventor： Vikas Rana

IPC: G11C11/4193 ,  G11C11/4195

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。

公开(公告)号：US07919983B1

公开(公告)日：2011-04-05

申请号：US12643244

申请日：2009-12-21

Applicant: Vikas Rana

Inventor： Vikas Rana

IPC: H03K19/0175

CPC classification number: H03K19/018528

Abstract: A level shifter for integrated circuits includes input stage transistors, reference stage transistors, a cascode stage coupled to the input stage and the reference stage transistors and a pair of comparators. The cascode stage generates a first cascode output and a second cascode output. The input stage transistors selectively conduct a low reference voltage as the first cascode output based on a pair of inputs provided to the input stage transistors. The reference stage transistors selectively conduct a high reference voltage as the second cascode output based on a first comparator output and a second comparator output. The pair of comparators generate the first and the second comparator outputs based on the first and the second cascode outputs.

Abstract translation: 用于集成电路的电平移位器包括输入级晶体管，参考级晶体管，耦合到输入级和参考级晶体管的共源共栅级和一对比较器。 共源共栅级产生第一共源共栅输出和第二共源共栅输出。 基于提供给输入级晶体管的一对输入，输入级晶体管选择性地将低参考电压作为第一共源共栅输出。 基于第一比较器输出和第二比较器输出，参考级晶体管选择性地传导高参考电压作为第二共源共栅输出。 该对比较器基于第一和第二共源共栅输出产生第一和第二比较器输出。

公开(公告)号：US07750689B1

公开(公告)日：2010-07-06

申请号：US12343773

申请日：2008-12-24

Applicant: Vikas Rana ,  Abhishek Lal ,  Promod Kumar

Inventor： Vikas Rana ,  Abhishek Lal ,  Promod Kumar

IPC: H03K3/00

CPC classification number: H03K3/356113 ,  H03K3/0375 ,  H03K3/356182

Abstract: The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level. The module further comprises a switching circuit that is operatively coupled to the driver output for controlling the passing of a high voltage with high current requirements.

Abstract translation: 本发明公开了一种在其驱动器输出级具有减小的应力的高压开关模块，其继而控制需要高电流驱动的晶体管的栅极。 开关模块包括负升压电路，延迟模块，上拉电路和下拉电路。 负升压电路感测逻辑输入信号的转变以产生控制信号。 第一上拉电路可操作地耦合到该控制信号，用于将驱动器输出从负电压切换到接地电压。 还有一个额外的延迟模块被配置为提供逻辑输入信号的延迟。 该延迟逻辑输入信号可操作地耦合到将驱动器的输出从GND到VDD的第二上拉级。 下拉电路可操作地耦合到负电梯，以将驱动器输出处的电压控制到负电平。 该模块还包括可操作地耦合到驱动器输出的开关电路，用于以高电流要求控制高电压的通过。