发明授权
US08462553B2 Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory
失效
单元阵列,用于高可缩放,字节可变的双晶体管FLOTOX EEPROM非易失性存储器
- 专利标题: Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory
- 专利标题(中): 单元阵列,用于高可缩放,字节可变的双晶体管FLOTOX EEPROM非易失性存储器
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申请号: US12930022申请日: 2010-12-23
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公开(公告)号: US08462553B2公开(公告)日: 2013-06-11
- 发明人: Peter Wung Lee , Fu-Chang Hsu
- 申请人: Peter Wung Lee , Fu-Chang Hsu
- 申请人地址: US CA San Jose
- 专利权人: Aplus Flash Technology, Inc.
- 当前专利权人: Aplus Flash Technology, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Saile Ackerman LLC
- 代理商 Stephen B. Ackerman; Billy Knowles
- 主分类号: G11C11/34
- IPC分类号: G11C11/34
摘要:
Two-transistor FLOTOX EEPROM cells are collected to form an alterable unit such as a byte. Each of the two-transistor FLOTOX EEPROM cells has a bit line connected to a drain of a select transistor of each of the two-transistor FLOTOX EEPROM cells and a source line placed in parallel with the bit line and connected to a source of a floating gate transistor of each of the two-transistor FLOTOX EEPROM cells. In a program operation, the bit lines are connected to a very large programming voltage level and the source lines are connected to a punch through inhibit voltage level. The punch through inhibit voltage level is approximately one half the very large programming voltage level. The lower drain-to-source voltage level permits the select transistor and the floating gate transistor to have smaller channel lengths and therefore a lower drain-to-source breakdown voltage.
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