Invention Grant
- Patent Title: Memory array error correction
- Patent Title (中): 存储器阵列纠错
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Application No.: US10934928Application Date: 2004-09-03
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Publication No.: US08464093B1Publication Date: 2013-06-11
- Inventor: Erik R. Swenson , Brian C. Edem , Thuan D. Nguyen , Khoi D. Vu
- Applicant: Erik R. Swenson , Brian C. Edem , Thuan D. Nguyen , Khoi D. Vu
- Applicant Address: US CA Santa Clara
- Assignee: Extreme Networks, Inc.
- Current Assignee: Extreme Networks, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman, LLP
- Main IPC: G06F11/10
- IPC: G06F11/10

Abstract:
A memory array comprises N+1 memory elements. N memory elements store data and one or more error check bits respectively derived from the stored data. A separate N+1 memory element stores parity bits generated from the data stored in the N memory elements. These parity bits are stored in. To recover from data errors, data in each N memory element are first checked using their respective error check bits. If faulty data are detected in one of the N memory elements, an exclusive-or operation is performed involving data in the remaining N−1 memory elements and parity bits in the N+1 memory element. This recovers the faulty data in the one memory element.
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