Memory array error correction
    1.
    发明授权
    Memory array error correction 有权
    存储器阵列纠错

    公开(公告)号:US08464093B1

    公开(公告)日:2013-06-11

    申请号:US10934928

    申请日:2004-09-03

    CPC classification number: G06F11/108 G06F11/1004 G06F11/1044

    Abstract: A memory array comprises N+1 memory elements. N memory elements store data and one or more error check bits respectively derived from the stored data. A separate N+1 memory element stores parity bits generated from the data stored in the N memory elements. These parity bits are stored in. To recover from data errors, data in each N memory element are first checked using their respective error check bits. If faulty data are detected in one of the N memory elements, an exclusive-or operation is performed involving data in the remaining N−1 memory elements and parity bits in the N+1 memory element. This recovers the faulty data in the one memory element.

    Abstract translation: 存储器阵列包括N + 1个存储元件。 N个存储器元件存储分别从存储的数据导出的数据和一个或多个错误校验位。 单独的N + 1个存储元件存储从存储在N个存储元件中的数据生成的奇偶校验位。 这些奇偶校验位被存储。为了从数据错误中恢复,首先使用各自的错误校验位来检查每个N个存储器元件中的数据。 如果在N个存储器元件之一中检测到有故障的数据,则执行涉及N + 1个存储元件中的剩余N-1个存储元件和奇偶校验位中的数据的异或运算。 这恢复了一个存储器元件中的故障数据。

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