发明授权
US08464125B2 Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
有权
用于可编程循环冗余校验（CRC）计算的指令集架构
- 专利标题： Instruction-set architecture for programmable cyclic redundancy check (CRC) computations
- 专利标题（中）： 用于可编程循环冗余校验（CRC）计算的指令集架构
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申请号： US12653249申请日： 2009-12-10
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公开(公告)号： US08464125B2公开(公告)日： 2013-06-11
- 发明人: Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
- 申请人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Trop, Pruner & Hu, P.C.
- 主分类号： H03M13/00
- IPC分类号： H03M13/00
摘要：
A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
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