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发明授权
US08466821B2 Delta sigma ADC 有权
Delta西格玛ADC

Delta sigma ADC
摘要：
A ΔΣADC is provided that is capable of suppressing increase of a circuit scale without losing noise shaping function even when a switching speed of a switch for performing time-division process is lower than a sampling rate of the ΔΣADC. For a code values provided by a comparator (105), the ΔΣADC (100) has a first storage section (106-1) and a second storage section (106-2) respectively for signal sequences (a first signal sequence and a second signal sequence) constituting a time-divisionally combined signal. Then, one of the two storage sections (i.e. the first storage section (106-1) and the second storage section (106-2)) that corresponds to a branch selection signal is configured to store the code value obtained from the comparator (105). On the other hand, one of the two storage sections (i.e. the first storage section (106-1) and the second storage section (106-2)) that is not the storage section corresponding to the branch selection signal is configured to hold the already stored code value.
摘要（中）：

提供了一种DeltaSigmaADC，即使当用于执行时分处理的开关的切换速度低于DeltaSigmaADC的采样率时，也能够抑制电路规模的增加而不失去噪声整形功能。 对于由比较器（105）提供的代码值，DeltaSigmaADC（100）具有分别用于信号序列的第一存储部分（106-1）和第二存储部分（106-2）（第一信号序列和第二信号 序列）构成时分组合信号。 然后，对应于分支选择信号的两个存储部分（即，第一存储部分（106-1）和第二存储部分（106-2））之一被配置为存储从比较器（105）获得的代码值 ）。 另一方面，不是与分支选择信号对应的存储部的两个存储部（即，第一存储部（106-1）和第二存储部106-2）中的一个被配置为保持 已经存储的代码值。

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