According to one embodiment, a semiconductor memory device includes a word line interconnect layer, a bit line interconnect layer and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction intersecting with the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar has a selector stacked film containing silicon, and a variable resistance film disposed on a side of the word lines or the bit lines. The selector stacked film has a different component-containing layer. The different component-containing layer is formed at one position in a region excluding ends on the sides of the word and bit lines, and contains a 14 group element having a larger atomic radius than an atomic radius of silicon.