发明授权
- 专利标题： High-speed receiver architecture
- 专利标题（中）： 高速接收机架构
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申请号： US12056084申请日： 2008-03-26
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公开(公告)号： US08483343B2公开(公告)日： 2013-07-09
- 发明人: Oscar E. Agazzi , Diego E. Crivelli , Hugo S. Carrer , Mario R. Hueda , German C. Luna , Carl Grace
- 申请人： Oscar E. Agazzi , Diego E. Crivelli , Hugo S. Carrer , Mario R. Hueda , German C. Luna , Carl Grace
- 申请人地址： US CA Irvine
- 专利权人： ClariPhy Communications, Inc.
- 当前专利权人： ClariPhy Communications, Inc.
- 当前专利权人地址： US CA Irvine
- 代理机构： Fenwick & West LLP
- 主分类号： H04L7/00
- IPC分类号： H04L7/00
摘要：
A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
公开/授权文献
- US20080240325A1 High-Speed Receiver Architecture 公开/授权日：2008-10-02
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