Invention Grant
- Patent Title: Method for forming an integrated circuit level by sequential tridimensional integration
- Patent Title (中): 通过连续三维积分形成集成电路电平的方法
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Application No.: US12794092Application Date: 2010-06-04
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Publication No.: US08486817B2Publication Date: 2013-07-16
- Inventor: Perceval Coudrain , Philippe Coronel , Nicolas Buffet
- Applicant: Perceval Coudrain , Philippe Coronel , Nicolas Buffet
- Applicant Address: FR Montrouge FR Crolles FR Paris
- Assignee: STMicroelectronics S.A.,STMicroelectronics (Crolles 2) SAS,Commissariat à l'Énergies Atomique et aux Énergies Alternatives
- Current Assignee: STMicroelectronics S.A.,STMicroelectronics (Crolles 2) SAS,Commissariat à l'Énergies Atomique et aux Énergies Alternatives
- Current Assignee Address: FR Montrouge FR Crolles FR Paris
- Agency: Wolf, Greenfield & Sacks, P.C.
- Priority: FR0953766 20090605
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/762 ; H01L21/28
Abstract:
A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.
Public/Granted literature
- US20100308411A1 METHOD FOR FORMING AN INTEGRATED CIRCUIT LEVEL BY SEQUENTIAL TRIDIMENSIONAL INTEGRATION Public/Granted day:2010-12-09
Information query
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