Invention Grant
- Patent Title: Distributing spare latch circuits in integrated circuit designs
- Patent Title (中): 在集成电路设计中分配备用锁存电路
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Application No.: US13315914Application Date: 2011-12-09
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Publication No.: US08490039B2Publication Date: 2013-07-16
- Inventor: Mitesh A. Agrawal , Santosh Balasubramanian , Pradeep N. Chatnahalli , Prasad Shivaram
- Applicant: Mitesh A. Agrawal , Santosh Balasubramanian , Pradeep N. Chatnahalli , Prasad Shivaram
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Richard Kotulak
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks.
Public/Granted literature
- US20130152029A1 DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS Public/Granted day:2013-06-13
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