公开(公告)号：US20130332137A1

公开(公告)日：2013-12-12

申请号：US13492399

申请日：2012-06-08

Applicant: Santosh Balasubramanian ,  Aaron C. Brown ,  David W. Cummings ,  Ambalath Matayambath Roopesh

Inventor： Santosh Balasubramanian ,  Aaron C. Brown ,  David W. Cummings ,  Ambalath Matayambath Roopesh

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F17/5031 ,  G06F2217/84

Abstract: A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.

Abstract translation: 计算机在集成电路设计的仿真模型中识别存储元件，其在使用仿真模型的集成电路设计的仿真期间被迫使其值被强制。 响应于识别存储元件，将存储元件和相关联的时钟信号的指示存储在数据库中。 响应于接收到在模拟期间指示存储元件的值的输入，通过参考数据库来确定参考相关联的时钟信号是否使该值的强制失效。 响应于参考相关联的时钟信号来确定输入值所表示的值的强制被确定，输出该值的强制被指示的指示。

公开(公告)号：US08490039B2

公开(公告)日：2013-07-16

申请号：US13315914

申请日：2011-12-09

Applicant: Mitesh A. Agrawal ,  Santosh Balasubramanian ,  Pradeep N. Chatnahalli ,  Prasad Shivaram

Inventor： Mitesh A. Agrawal ,  Santosh Balasubramanian ,  Pradeep N. Chatnahalli ,  Prasad Shivaram

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks.

Abstract translation: 提供了在集成电路设计中将备用锁存电路分配给逻辑块的方法。 一种方法包括确定设计中的逻辑块，并且基于逻辑块的相应属性来确定和确定逻辑块中备用锁存电路的分配。 该方法还包括根据与逻辑块对应的本地时钟缓冲器，根据所确定的分配将备用锁存电路置于设计中。

公开(公告)号：US20130159487A1

公开(公告)日：2013-06-20

申请号：US13415844

申请日：2012-03-09

Applicant: Parveen Kumar Patel ,  David A. Dion ,  Corey Sanders ,  Santosh Balasubramanian ,  Deepak Bansal ,  Vladimir Petter ,  Daniel Brown Benediktson

Inventor： Parveen Kumar Patel ,  David A. Dion ,  Corey Sanders ,  Santosh Balasubramanian ,  Deepak Bansal ,  Vladimir Petter ,  Daniel Brown Benediktson

IPC: G06F15/173

CPC classification number: H04L67/1031 ,  G06F2209/503 ,  H04L61/103 ,  H04L61/2007 ,  H04L67/1034

Abstract: The movement of a Virtual IP (VIP) address from cluster node to cluster node is coordinated via a load balancer. All or a subset of the nodes in a load balancer cluster may be configured as possible hosts for the VIP. The load balancer directs VIP traffic to the Dedicated IP (DIP) address for the cluster node that responds affirmatively to periodic health probe messages. In this way, a VIP failover is executed when a first node stops responding to probe messages, and a second node starts to respond to the periodic health probe messages. In response to an affirmative probe response from a new node, the load balancer immediately directs the VIP traffic to the new node's DIP. The probe messages may be configured to identify which nodes are currently responding affirmatively to probes to assist the nodes in determining when to execute a failover.

Abstract translation: 从集群节点到集群节点的虚拟IP（VIP）地址的移动通过负载平衡器进行协调。 负载平衡器集群中的所有或一部分节点可能被配置为VIP的可能主机。 负载平衡器将VIP流量引导到针对周期性健康探测消息做出肯定响应的群集节点的专用IP（DIP）地址。 以这种方式，当第一节点停止响应探测消息时，执行VIP故障切换，并且第二节点开始响应周期性健康探测消息。 响应来自新节点的肯定的探测响应，负载平衡器立即将VIP流量引导到新节点的DIP。 探测消息可以被配置为识别哪些节点当前正确地响应于探测器来帮助节点确定何时执行故障转移。

公开(公告)号：US20130152029A1

公开(公告)日：2013-06-13

申请号：US13315914

申请日：2011-12-09

Applicant: Mitesh A. AGRAWAL ,  Santosh BALASUBRAMANIAN ,  Pradeep N. CHATNAHALLI ,  Prasad SHIVARAM

Inventor： Mitesh A. AGRAWAL ,  Santosh BALASUBRAMANIAN ,  Pradeep N. CHATNAHALLI ,  Prasad SHIVARAM

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks.

Abstract translation: 提供了在集成电路设计中将备用锁存电路分配给逻辑块的方法。 一种方法包括确定设计中的逻辑块，并且基于逻辑块的相应属性来确定和确定逻辑块中备用锁存电路的分配。 该方法还包括根据与逻辑块对应的本地时钟缓冲器，根据所确定的分配将备用锁存电路置于设计中。